diff options
| author | Benjamin Herrenschmidt <benh@kernel.crashing.org> | 2020-08-04 23:02:14 +0530 |
|---|---|---|
| committer | Oliver O'Halloran <oohall@gmail.com> | 2020-08-07 16:00:20 +1000 |
| commit | 1df445d7a278b0b5fb40e9f2641d28ccfae51813 (patch) | |
| tree | 8362820b0a355f04ee3ae5a99d341c7fa14356d4 /hw | |
| parent | 2d065e249f78e11ddeca0c84920b28a7ca4f8ee1 (diff) | |
| download | skiboot-1df445d7a278b0b5fb40e9f2641d28ccfae51813.zip skiboot-1df445d7a278b0b5fb40e9f2641d28ccfae51813.tar.gz skiboot-1df445d7a278b0b5fb40e9f2641d28ccfae51813.tar.bz2 | |
xive: Set the fused core mode properly
Set or clear the fused core mode bit in the XIVE inits
properly. While HostBoot is supposed to do it, I prefer
not depending on it doing the right thing, since we already
configure that register ourselves anyway.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Michael Neuling <mikey@neuling.org>
Signed-off-by: Vaidyanathan Srinivasan <svaidy@linux.ibm.com>
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
Diffstat (limited to 'hw')
| -rw-r--r-- | hw/xive.c | 4 |
1 files changed, 4 insertions, 0 deletions
@@ -1531,6 +1531,10 @@ static bool xive_config_init(struct xive *x) val |= PC_TCTXT_CFG_LGS_EN; /* Disable pressure relief as we hijack the field in the VPs */ val &= ~PC_TCTXT_CFG_STORE_ACK; + if (this_cpu()->is_fused_core) + val |= PC_TCTXT_CFG_FUSE_CORE_EN; + else + val &= ~PC_TCTXT_CFG_FUSE_CORE_EN; xive_regw(x, PC_TCTXT_CFG, val); xive_dbg(x, "PC_TCTXT_CFG=%016llx\n", val); |