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author | Frederic Barrat <fbarrat@linux.ibm.com> | 2021-01-29 10:22:07 +0100 |
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committer | Vasant Hegde <hegdevasant@linux.vnet.ibm.com> | 2021-02-04 14:02:34 +0530 |
commit | 15b93a301509ba7813343540e25b47ba395674b9 (patch) | |
tree | 6cdc4bf8dc52d967129f499ae37dace814ce9a23 /hw | |
parent | bb4530b1f4889082dae38b562b8b7cff63ba5855 (diff) | |
download | skiboot-15b93a301509ba7813343540e25b47ba395674b9.zip skiboot-15b93a301509ba7813343540e25b47ba395674b9.tar.gz skiboot-15b93a301509ba7813343540e25b47ba395674b9.tar.bz2 |
phb4: Disable TCE cache line buffer
This patch implements a circumvention for HW557787. It disables the
TCE cache line buffer as, under heavy loads, there's a possibility of
an entry being re-allocated incorrectly.
Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
Diffstat (limited to 'hw')
-rw-r--r-- | hw/phb4.c | 1 |
1 files changed, 1 insertions, 0 deletions
@@ -5303,6 +5303,7 @@ static void phb4_init_hw(struct phb4 *p) /* Init_17 - PHB Control */ val = PHB_CTRLR_IRQ_PGSZ_64K; + val |= PHB_CTRLR_TCE_CLB_DISABLE; // HW557787 circumvention val |= SETFIELD(PHB_CTRLR_TVT_ADDR_SEL, 0ull, TVT_2_PER_PE); if (PHB4_CAN_STORE_EOI(p)) val |= PHB_CTRLR_IRQ_STORE_EOI; |