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| author | Alistair Popple <alistair@popple.id.au> | 2015-09-15 11:20:05 +1000 |
|---|---|---|
| committer | Stewart Smith <stewart@linux.vnet.ibm.com> | 2015-10-08 14:17:00 +1100 |
| commit | b4315f5520cb99312e139d55289a012af14ad042 (patch) | |
| tree | e009d4fd14cda6c4ed00ac2dc32bcdb7d305b297 /hw | |
| parent | dc3d17ac940fe1e0b2723a31d171ab47fd68fd47 (diff) | |
| download | skiboot-b4315f5520cb99312e139d55289a012af14ad042.zip skiboot-b4315f5520cb99312e139d55289a012af14ad042.tar.gz skiboot-b4315f5520cb99312e139d55289a012af14ad042.tar.bz2 | |
interrupts: Convert P8 IRQ assignment to functions
Interrupts on P8 are currently hard-coded using macros in
include/interrupts.h. The new P8NVL processor has an extra PHB meaning
it supports 4 PHBs in total which leads to the following assert fail
when booting P8NVL based systems:
[6614913194,3] register IRQ source overlap !
[6620562844,3] new: 2000..27f7 old: 2000..27f7
[6870377440,0] Assert fail: core/interrupts.c:67:0
This patch converts the existing macros to function calls so that
different platforms can support extra PHBs at the expense of a reduced
maximum number of chips.
Signed-off-by: Alistair Popple <alistair@popple.id.au>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
Diffstat (limited to 'hw')
| -rw-r--r-- | hw/phb3.c | 18 |
1 files changed, 9 insertions, 9 deletions
@@ -1550,8 +1550,8 @@ static int64_t phb3_msi_get_xive(void *data, uint32_t chip, index, irq; uint64_t ive; - chip = P8_IRQ_TO_CHIP(isn); - index = P8_IRQ_TO_PHB(isn); + chip = p8_irq_to_chip(isn); + index = p8_irq_to_phb(isn); irq = PHB3_IRQ_NUM(isn); if (chip != p->chip_id || @@ -1580,8 +1580,8 @@ static int64_t phb3_msi_set_xive(void *data, uint64_t *cache, ive_num, data64, m_server, m_prio; uint32_t *ive; - chip = P8_IRQ_TO_CHIP(isn); - index = P8_IRQ_TO_PHB(isn); + chip = p8_irq_to_chip(isn); + index = p8_irq_to_phb(isn); ive_num = PHB3_IRQ_NUM(isn); if (p->state == PHB3_STATE_BROKEN || !p->tbl_rtt) @@ -1642,8 +1642,8 @@ static int64_t phb3_lsi_get_xive(void *data, uint32_t chip, index, irq; uint64_t lxive; - chip = P8_IRQ_TO_CHIP(isn); - index = P8_IRQ_TO_PHB(isn); + chip = p8_irq_to_chip(isn); + index = p8_irq_to_phb(isn); irq = PHB3_IRQ_NUM(isn); if (chip != p->chip_id || @@ -1668,8 +1668,8 @@ static int64_t phb3_lsi_set_xive(void *data, uint32_t chip, index, irq, entry; uint64_t lxive; - chip = P8_IRQ_TO_CHIP(isn); - index = P8_IRQ_TO_PHB(isn); + chip = p8_irq_to_chip(isn); + index = p8_irq_to_phb(isn); irq = PHB3_IRQ_NUM(isn); if (p->state == PHB3_STATE_BROKEN) @@ -4479,7 +4479,7 @@ static void phb3_probe_pbcq(struct dt_node *pbcq) /* Set the interrupt routing stuff, 8 relevant bits in mask * (11 bits per PHB) */ - val = P8_CHIP_IRQ_PHB_BASE(gcid, pno); + val = p8_chip_irq_phb_base(gcid, pno); val = (val << 45); xscom_write(gcid, pe_xscom + 0x1a, val); xscom_write(gcid, pe_xscom + 0x1b, 0xff00000000000000ul); |