Fix spelling mistakes

See https://github.com/lucasdemarchi/codespel

Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>

9 files changed, 15 insertions, 15 deletions

diff --git a/hw/ast-bmc/ast-io.c b/hw/ast-bmc/ast-io.c
index 08ce99d..a3c5c9f 100644
--- a/hw/ast-bmc/ast-io.c
+++ b/hw/ast-bmc/ast-io.c
@@ -27,7 +27,7 @@
  * using FW space as normal memory space is limited to byte accesses
  * to a fixed 256M window, while FW space allows us to use different
  * access sizes and to control the IDSEL bits which essentially enable
- * a full 4G addres space.
+ * a full 4G address space.
  *
  * The way FW accesses map onto AHB is controlled via two registers
  * in the BMC's LPC host controller:
@@ -79,7 +79,7 @@
  *
  * For the time being, we use the iLPC->AHB for everything except
  * pnor accesses. In the long run, we will reconfigure the LPC->AHB
- * to provide more direct access to all of the BMC addres space but
+ * to provide more direct access to all of the BMC address space but
  * we'll only do that after the boot script/program on the BMC is
  * updated to restore the bridge to a state compatible with the SBE
  * expectations on boot.
diff --git a/hw/fsp/fsp-dump.c b/hw/fsp/fsp-dump.c
index c57d730..ae5bfee 100644
--- a/hw/fsp/fsp-dump.c
+++ b/hw/fsp/fsp-dump.c
@@ -18,7 +18,7 @@
 /*
  * Dump support:
  *  We get dump notification from different sources:
- *   - During system intialization via HDAT
+ *   - During system initialization via HDAT
  *   - During FSP reset/reload (FipS dump)
  *   - Dump available notification MBOX command (0xCE, 0x78, 0x00)
  *
diff --git a/hw/fsp/fsp-epow.c b/hw/fsp/fsp-epow.c
index 79171c5..df36c46 100644
--- a/hw/fsp/fsp-epow.c
+++ b/hw/fsp/fsp-epow.c
@@ -129,7 +129,7 @@ static int64_t fsp_opal_get_epow_status(int16_t *out_epow,
 
 	/*
 	 * There can be situations where the host and the Sapphire versions
-	 * dont match with eact other and hence the expected system EPOW status
+	 * don't match with eact other and hence the expected system EPOW status
 	 * details. Newer hosts might be expecting status for more number of EPOW
 	 * sub classes which Sapphire may not know about and older hosts might be
 	 * expecting status for EPOW sub classes which is a subset of what
diff --git a/hw/fsp/fsp-leds.c b/hw/fsp/fsp-leds.c
index dba7b35..c20049e 100644
--- a/hw/fsp/fsp-leds.c
+++ b/hw/fsp/fsp-leds.c
@@ -175,7 +175,7 @@ static void compute_encl_status_cec(struct fsp_led_data *encl_led)
 		if (!strstr(led->loc_code, encl_led->loc_code))
 			continue;
 
-		/* Dont count the enclsure LED itself */
+		/* Don't count the enclsure LED itself */
 		if (!strcmp(led->loc_code, encl_led->loc_code))
 			continue;
 
@@ -350,7 +350,7 @@ static bool sai_update_notification(struct fsp_msg *msg)
 
 /*
  * Update both the local LED lists to reflect upon led state changes
- * occured with the recent SPCN command. Subsequent LED requests will
+ * occurred with the recent SPCN command. Subsequent LED requests will
  * be served with these updates changed to the list.
  */
 static void update_led_list(char *loc_code, u32 led_state, u32 excl_bit)
@@ -751,7 +751,7 @@ static u32 fsp_push_data_to_tce(struct fsp_led_data *led, u8 *out_data,
 
 	/*
 	 * Check for outbound buffer overflow. If there are still
-	 * more LEDs to be sent across to FSP, dont send, ignore.
+	 * more LEDs to be sent across to FSP, don't send, ignore.
 	 */
 	if ((total_size + lcode.size) > PSI_DMA_LOC_COD_BUF_SZ)
 		return 0;
@@ -1582,7 +1582,7 @@ static void fsp_process_leds_data(u16 len)
 	 * Process the entire captured data from the last command
 	 *
 	 * TCE mapped 'led_buffer' contains the fsp_led_data structure
-	 * one after the other till the total lenght 'len'.
+	 * one after the other till the total length 'len'.
 	 *
 	 */
 	buf = led_buffer;
diff --git a/hw/fsp/fsp-mem-err.c b/hw/fsp/fsp-mem-err.c
index 019e737..526afaf 100644
--- a/hw/fsp/fsp-mem-err.c
+++ b/hw/fsp/fsp-mem-err.c
@@ -351,7 +351,7 @@ static bool fsp_mem_err_msg(u32 cmd_sub_mod, struct fsp_msg *msg)
 		/*
 		 * We get the memory relilence command from FSP for
 		 * correctable/Uncorrectable/scrub UE errors with real
-		 * address of 4K memory page in which the error occured.
+		 * address of 4K memory page in which the error occurred.
 		 */
 		paddr_start = *((u64 *)&msg->data.words[0]);
 		printf("Got memory resilience error message for "
diff --git a/hw/fsp/fsp.c b/hw/fsp/fsp.c
index a23384c..c80fff7 100644
--- a/hw/fsp/fsp.c
+++ b/hw/fsp/fsp.c
@@ -109,7 +109,7 @@ static u64 fsp_hir_timeout;
 
 /*
  * We keep track on last logged values for some things to print only on
- * value changes, but also to releive pressure on the tracer which
+ * value changes, but also to relieve pressure on the tracer which
  * doesn't do a very good job at detecting repeats when called from
  * many different CPUs
  */
diff --git a/hw/ipmi/ipmi-watchdog.c b/hw/ipmi/ipmi-watchdog.c
index 498d4c6..7dfb0c0 100644
--- a/hw/ipmi/ipmi-watchdog.c
+++ b/hw/ipmi/ipmi-watchdog.c
@@ -40,9 +40,9 @@
 #define WDT_TIMEOUT		600
 
 /* How often to reset the timer using schedule_timer(). Too short and
-we risk accidently resetting the system due to opal_run_pollers() not
+we risk accidentally resetting the system due to opal_run_pollers() not
 being called in time, too short and we waste time resetting the wdt
-more frequently than neccessary. */
+more frequently than necessary. */
 #define WDT_MARGIN		300
 
 static struct timer wdt_timer;
diff --git a/hw/p5ioc2-phb.c b/hw/p5ioc2-phb.c
index e3f546e..06c2cc2 100644
--- a/hw/p5ioc2-phb.c
+++ b/hw/p5ioc2-phb.c
@@ -906,7 +906,7 @@ static void p5ioc2_phb_hwinit(struct p5ioc2_phb *p)
 	 * wired on the motherboard). I set things up based on
 	 * the values I read on a Juno machine. We setup the BPR
 	 * with the various timeouts etc... as well based one
-	 * similarily captured values
+	 * similarly captured values
 	 */
 	if (p->is_pcie) {
 		out_be32(p->regs + CAP_AER, 0x04000000);
diff --git a/hw/p8-i2c.c b/hw/p8-i2c.c
index 775e777..dfb26d4 100644
--- a/hw/p8-i2c.c
+++ b/hw/p8-i2c.c
@@ -294,7 +294,7 @@ static bool p8_i2c_has_irqs(struct p8_i2c_master *master)
 	/* The i2c interrurpt was only added to Murano DD2.1 and Venice
 	 * DD2.0. When operating without interrupts, we need to bump the
 	 * timeouts as we rely solely on the polls from Linux which can
-	 * be up to 2s appart !
+	 * be up to 2s apart !
 	 *
 	 * Also we don't have interrupts for the Centaur i2c.
 	 */
@@ -466,7 +466,7 @@ static void p8_i2c_status_error(struct p8_i2c_master_port *port,
 	 */
 	if (!(status & I2C_STAT_NACK_RCVD_ERR)) {
 		log_simple_error(&e_info(OPAL_RC_I2C_TRANSFER),
-				 "I2C: Transfer error occured\n");
+				 "I2C: Transfer error occurred\n");
 		p8_i2c_print_debug_info(port, req);
 	}