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authorCédric Le Goater <clg@fr.ibm.com>2015-03-09 21:56:13 +0100
committerStewart Smith <stewart@linux.vnet.ibm.com>2015-03-24 18:22:55 +1100
commit2d8952a581a857f010df38422ed7803d8be64061 (patch)
treec3064c07e16f0004c25c545c105acd90939b02cc /hw
parent132e593400f959074f72cf066e3e99c8cd8d7b82 (diff)
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dts: add support to read the core temperatures
This patch adds a new sensor family for Digital Temperature Sensors and a new resource class to capture the core temperatures. Each core has four DTS located in different zones (LSU, ISU, FXU, L3). The max of the four temperatures is computed and returned for the core as well as a global trip point value. This is based on the meltbox tool. Signed-off-by: Cédric Le Goater <clg@fr.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
Diffstat (limited to 'hw')
-rw-r--r--hw/Makefile.inc1
-rw-r--r--hw/dts.c165
2 files changed, 166 insertions, 0 deletions
diff --git a/hw/Makefile.inc b/hw/Makefile.inc
index 395a65f..8a67d75 100644
--- a/hw/Makefile.inc
+++ b/hw/Makefile.inc
@@ -6,6 +6,7 @@ HW_OBJS += homer.o slw.o occ.o fsi-master.o centaur.o
HW_OBJS += nx.o nx-rng.o nx-crypto.o nx-842.o
HW_OBJS += p7ioc.o p7ioc-inits.o p7ioc-phb.o p5ioc2.o p5ioc2-phb.o
HW_OBJS += phb3.o sfc-ctrl.o fake-rtc.o bt.o p8-i2c.o prd.o
+HW_OBJS += dts.o
HW=hw/built-in.o
include $(SRC)/hw/fsp/Makefile.inc
diff --git a/hw/dts.c b/hw/dts.c
new file mode 100644
index 0000000..c89da51
--- /dev/null
+++ b/hw/dts.c
@@ -0,0 +1,165 @@
+/* Copyright 2013-2015 IBM Corp.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+ * implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <xscom.h>
+#include <chip.h>
+#include <sensor.h>
+#include <dts.h>
+#include <skiboot.h>
+
+/* Per core Digital Thermal Sensors */
+#define EX_THERM_DTS_RESULT0 0x10050000
+#define EX_THERM_DTS_RESULT1 0x10050001
+
+/* Per core Digital Thermal Sensors control registers */
+#define EX_THERM_MODE_REG 0x1005000F
+#define EX_THERM_CONTROL_REG 0x10050012
+#define EX_THERM_ERR_STATUS_REG 0x10050013
+
+struct dts {
+ uint8_t valid;
+ uint8_t trip;
+ int16_t temp;
+};
+
+
+/* Therm mac result masking for DTS (result(0:15)
+ * 0:3 - 0x0
+ * 4:11 - Temperature in degrees C
+ * 12:13 - trip bits: 00 - no trip; 01 - warning; 10 - critical; 11 - fatal
+ * 14 - spare
+ * 15 - valid
+ */
+static void dts_decode_one_dts(uint16_t raw, struct dts *dts)
+{
+ /*
+ * The value is both signed and unsigned :-) 0xff could be
+ * either 255C or -1C, so for now we treat this as unsigned
+ * which is sufficient for our purpose. We could try to be
+ * a bit smarter and treat it as signed for values between
+ * -10 and 0 and unsigned to 239 or something like that...
+ */
+ dts->valid = raw & 1;
+ if (dts->valid) {
+ dts->temp = (raw >> 4) & 0xff;
+ dts->trip = (raw >> 2) & 0x3;
+ } else {
+ dts->temp = 0;
+ dts->trip = 0;
+ }
+}
+
+/* Different sensor locations */
+#define P8_CT_ZONE_LSU 0
+#define P8_CT_ZONE_ISU 1
+#define P8_CT_ZONE_FXU 2
+#define P8_CT_ZONE_L3C 3
+#define P8_CT_ZONES 4
+
+/*
+ * Returns the temperature as the max of all 4 zones and a global trip
+ * attribute.
+ */
+static int dts_read_core_temp(uint32_t pir, struct dts *dts)
+{
+ int32_t chip_id = pir_to_chip_id(pir);
+ int32_t core = pir_to_core_id(pir);
+ uint64_t dts0, dts1;
+ struct dts temps[P8_CT_ZONES];
+ int i;
+ int rc;
+
+ rc = xscom_read(chip_id, XSCOM_ADDR_P8_EX(core, EX_THERM_DTS_RESULT0),
+ &dts0);
+ if (rc)
+ return rc;
+
+ rc = xscom_read(chip_id, XSCOM_ADDR_P8_EX(core, EX_THERM_DTS_RESULT1),
+ &dts1);
+ if (rc)
+ return rc;
+
+ dts_decode_one_dts(dts0 >> 48, &temps[P8_CT_ZONE_LSU]);
+ dts_decode_one_dts(dts0 >> 32, &temps[P8_CT_ZONE_ISU]);
+ dts_decode_one_dts(dts0 >> 16, &temps[P8_CT_ZONE_FXU]);
+ dts_decode_one_dts(dts1 >> 48, &temps[P8_CT_ZONE_L3C]);
+
+ for (i = 0; i < P8_CT_ZONES; i++) {
+ int16_t t = temps[i].temp;
+
+ if (!temps[i].valid)
+ continue;
+
+ /* keep the max temperature of all 4 sensors */
+ if (t > dts->temp)
+ dts->temp = t;
+
+ dts->valid++;
+ dts->trip |= temps[i].trip;
+ }
+
+ prlog(PR_TRACE, "DTS: Chip %x Core %x temp:%dC trip:%x\n",
+ chip_id, core, dts->temp, dts->trip);
+ return 0;
+}
+
+/*
+ * DTS sensor class ids. Only one for the moment: the core
+ * temperature.
+ */
+enum sensor_dts_class {
+ SENSOR_DTS_CORE_TEMP,
+ /* To be continued */
+};
+
+/*
+ * Attributes for the core temperature sensor
+ */
+enum {
+ SENSOR_DTS_ATTR_TEMP_MAX,
+ SENSOR_DTS_ATTR_TEMP_TRIP
+};
+
+int64_t dts_sensor_read(uint32_t sensor_hndl, uint32_t *sensor_data)
+{
+ uint8_t attr = sensor_get_attr(sensor_hndl);
+ uint32_t rid = sensor_get_rid(sensor_hndl);
+ struct dts dts;
+ int64_t rc;
+
+ if (attr > SENSOR_DTS_ATTR_TEMP_TRIP)
+ return OPAL_PARAMETER;
+
+ memset(&dts, 0, sizeof(struct dts));
+
+ switch (sensor_get_frc(sensor_hndl) & ~SENSOR_DTS) {
+ case SENSOR_DTS_CORE_TEMP:
+ rc = dts_read_core_temp(rid, &dts);
+ break;
+ default:
+ rc = OPAL_PARAMETER;
+ break;
+ }
+ if (rc)
+ return rc;
+
+ if (attr == SENSOR_DTS_ATTR_TEMP_MAX)
+ *sensor_data = dts.temp;
+ else if (attr == SENSOR_DTS_ATTR_TEMP_TRIP)
+ *sensor_data = dts.trip;
+
+ return 0;
+}