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| author | Ananth N Mavinakayanahalli <ananth@in.ibm.com> | 2015-03-12 16:43:37 +0530 |
|---|---|---|
| committer | Stewart Smith <stewart@linux.vnet.ibm.com> | 2015-03-17 17:45:23 +1100 |
| commit | 5e10de0c32edc997407ef1911946f700e30ffd5e (patch) | |
| tree | 5a151b9f5abc1ae126a85160ea435c31dc4d0571 /hw | |
| parent | 8848bedba0a1cd306653c2365b757a840119aa1f (diff) | |
| download | skiboot-5e10de0c32edc997407ef1911946f700e30ffd5e.zip skiboot-5e10de0c32edc997407ef1911946f700e30ffd5e.tar.gz skiboot-5e10de0c32edc997407ef1911946f700e30ffd5e.tar.bz2 | |
fsp: Fix FSP irq initialization on PSIHBCR for resets
During Reset/Reload, we currently enable FSP interrupts on PSIHBCR
even before the DISR handshake is complete. Fix that.
Signed-off-by: Ananth N Mavinakayanahalli <ananth@in.ibm.com>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
Diffstat (limited to 'hw')
| -rw-r--r-- | hw/fsp/fsp.c | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/hw/fsp/fsp.c b/hw/fsp/fsp.c index fdf175a..779eef9 100644 --- a/hw/fsp/fsp.c +++ b/hw/fsp/fsp.c @@ -722,6 +722,8 @@ static void fsp_handle_errors(struct fsp *fsp) /* Also clear R&R complete bit in DISR */ fsp_wreg(fsp, FSP_DISR_REG, FSP_DISR_FSP_RR_COMPLETE); + + psi_enable_fsp_interrupt(psi); } } @@ -1859,7 +1861,6 @@ static void fsp_update_links_states(struct fsp *fsp) fiop = &fsp->iopath[fsp->active_iopath]; psi_init_for_fsp(fiop->psi); fsp_init_mbox(fsp); - psi_enable_fsp_interrupt(fiop->psi); } } @@ -1911,6 +1912,7 @@ static void fsp_create_fsp(struct dt_node *fsp_node) fsp_init_links(fsp_node); fsp_update_links_states(fsp); + psi_enable_fsp_interrupt(fsp->iopath[fsp->active_iopath].psi); } static void fsp_opal_poll(void *data __unused) |