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| author | Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com> | 2015-03-11 16:00:16 +0530 |
|---|---|---|
| committer | Stewart Smith <stewart@linux.vnet.ibm.com> | 2015-03-26 11:12:18 +1100 |
| commit | 2c6f80c7fd80edcd29b9ced904c104d5b3e83e99 (patch) | |
| tree | 474b82651a5b21ba25ba93e8cc506d9f4e19eba2 /hw | |
| parent | 28160facbc16b87d155804ecfd3e4bb3ba78fd27 (diff) | |
| download | skiboot-2c6f80c7fd80edcd29b9ced904c104d5b3e83e99.zip skiboot-2c6f80c7fd80edcd29b9ced904c104d5b3e83e99.tar.gz skiboot-2c6f80c7fd80edcd29b9ced904c104d5b3e83e99.tar.bz2 | |
opal: Recover from TB residue error.
Handle TB residue error reported through HMER[bit 5] and TFMR bit 45
i.e tb_residu_err. For recovery, reset TB register with all zeros and
then clear tb errors by writing 1 to TFMR bit 45 and 24. Clearing TB error
bits from TFMR would set the time state machine to RESET state and then
fall through existing code path which reloads the TB with TOD value and
get TB running.
To inject TB parity error issue:
$ putscom pu.ex 10013281 0003080000000000 -all
Signed-off-by: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
Diffstat (limited to 'hw')
| -rw-r--r-- | hw/chiptod.c | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/hw/chiptod.c b/hw/chiptod.c index e64f239..c7de0a4 100644 --- a/hw/chiptod.c +++ b/hw/chiptod.c @@ -648,6 +648,14 @@ static bool tfmr_recover_tb_errors(uint64_t tfmr) if (tfmr & SPR_TFMR_TB_MISSING_STEP) tfmr_reset_error |= SPR_TFMR_TB_MISSING_STEP; + if (tfmr & SPR_TFMR_TB_RESIDUE_ERR) { + /* To recover TB residue error, reset the TB register. */ + mtspr(SPR_TBWU, 0); + mtspr(SPR_TBWL, 0); + + /* write 1 to bit 45 to clear the error */ + tfmr_reset_error |= SPR_TFMR_TB_RESIDUE_ERR; + } mtspr(SPR_TFMR, tfmr_reset_error); /* We have to write "Clear TB Errors" again */ @@ -700,6 +708,7 @@ int chiptod_recover_tb_errors(void) * clear it. */ if ((tfmr & SPR_TFMR_TB_MISSING_STEP) || + (tfmr & SPR_TFMR_TB_RESIDUE_ERR) || (tfmr & SPR_TFMR_TB_MISSING_SYNC)) { if (!tfmr_recover_tb_errors(tfmr)) { rc = 0; |