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| author | Nicholas Piggin <npiggin@gmail.com> | 2019-01-08 00:04:28 +1000 |
|---|---|---|
| committer | Stewart Smith <stewart@linux.ibm.com> | 2019-02-13 14:36:44 +1100 |
| commit | 5d86cebd53683d055f039dbecf3f74fb0084ea83 (patch) | |
| tree | c9c4c9e9844643ca4f73ca686d1c4ec05d2287ee /hw | |
| parent | 22524e9017445a08d63733ae5a8c75d9126bdb28 (diff) | |
| download | skiboot-5d86cebd53683d055f039dbecf3f74fb0084ea83.zip skiboot-5d86cebd53683d055f039dbecf3f74fb0084ea83.tar.gz skiboot-5d86cebd53683d055f039dbecf3f74fb0084ea83.tar.bz2 | |
core/exceptions: implement support for MCE interrupts in powersave
The ISA specifies that MCE interrupts in power saving modes will enter
at 0x200 with powersave bits in SRR1 set. This is not currently
supported properly, the MCE will just happen like a normal interrupt,
but GPRs could be lost, which would lead to crashes (e.g., r1, r2, r13
etc).
So check the power save bits similarly to the sreset vector, and
handle this properly.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
Diffstat (limited to 'hw')
0 files changed, 0 insertions, 0 deletions