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| author | Cédric Le Goater <clg@kaod.org> | 2020-06-12 13:37:23 +0200 |
|---|---|---|
| committer | Oliver O'Halloran <oohall@gmail.com> | 2020-06-30 11:47:38 +1000 |
| commit | 2476b5b5ebf5d664b8c260eeaae80b6a32174218 (patch) | |
| tree | 8c4af47b129a91f50dfd0f136cd3774facf23e36 /hw/xive.c | |
| parent | 65cd7f293b743c6fef336186f6e69332e5f4d1f9 (diff) | |
| download | skiboot-2476b5b5ebf5d664b8c260eeaae80b6a32174218.zip skiboot-2476b5b5ebf5d664b8c260eeaae80b6a32174218.tar.gz skiboot-2476b5b5ebf5d664b8c260eeaae80b6a32174218.tar.bz2 | |
xive/p9: Clarify the global IRQ number encoding
On P9, the global IRQ number is limited to 24 bits because the XICS
emulation encodes the CPPR value in the top 8 bits. The following
4 bits are used to encode the XIVE block number, which leaves 20 bits
for the interrupt index number. Introduce a definition reflecting the
size of this bitfield and check that number of interrupts per chip is
not overflowing our encoding.
Reviewed-by: Gustavo Romero <gromero@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
Diffstat (limited to 'hw/xive.c')
| -rw-r--r-- | hw/xive.c | 19 |
1 files changed, 13 insertions, 6 deletions
@@ -498,13 +498,20 @@ static uint32_t xive_chip_to_block(uint32_t chip_id) * corresponding escalation descriptor. * * Global interrupt numbers for non-escalation interrupts are thus - * limited to 24 bits which is necessary for our XICS emulation since - * the top 8 bits are reserved for the CPPR value. - * + * limited to 24 bits because the XICS emulation encodes the CPPR + * value in the top (MSB) 8 bits. Hence, 4 bits are left for the XIVE + * block number and the remaining 20 bits for the interrupt index + * number. */ -#define GIRQ_TO_BLK(__g) (((__g) >> 20) & 0xf) -#define GIRQ_TO_IDX(__g) ((__g) & 0x000fffff) -#define BLKIDX_TO_GIRQ(__b,__i) (((uint32_t)(__b)) << 20 | (__i)) +#define INT_SHIFT 20 + +#if XIVE_INT_ORDER > INT_SHIFT +#error "Too many ESBs for IRQ encoding" +#endif + +#define GIRQ_TO_BLK(__g) (((__g) >> INT_SHIFT) & 0xf) +#define GIRQ_TO_IDX(__g) ((__g) & ((1 << INT_SHIFT) - 1)) +#define BLKIDX_TO_GIRQ(__b,__i) (((uint32_t)(__b)) << INT_SHIFT | (__i)) #define GIRQ_IS_ESCALATION(__g) ((__g) & 0x01000000) #define MAKE_ESCALATION_GIRQ(__b,__i)(BLKIDX_TO_GIRQ(__b,__i) | 0x01000000) |