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author | Haren Myneni <haren@linux.vnet.ibm.com> | 2019-10-26 01:47:35 -0700 |
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committer | Oliver O'Halloran <oohall@gmail.com> | 2019-11-05 19:39:16 +1100 |
commit | ad8cdd0f83bf55e9717326afb7af6eeedb33e031 (patch) | |
tree | c1751e19b530eb692712c6ab6db2ebef2aa2f322 /hw/vas.c | |
parent | c3bfa320955967c943348dc526828de3d278fdbc (diff) | |
download | skiboot-ad8cdd0f83bf55e9717326afb7af6eeedb33e031.zip skiboot-ad8cdd0f83bf55e9717326afb7af6eeedb33e031.tar.gz skiboot-ad8cdd0f83bf55e9717326afb7af6eeedb33e031.tar.bz2 |
VAS: Alloc IRQ and port address for each VAS instance
Setup IRQ and trigger port for each VAS instance. Export these
values through device-tree with 'interrupts' and 'ibm,vas-port'
properties in each VAS device node. Kernel setup IRQ and register
port address for each send window.
Enable 'vas-user-space' NVRAM config to allocate IRQ sources and
provide 'interrupts' property.
nvram -p ibm,skiboot --update-config vas-user-space=enable
Signed-off-by: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com>
Signed-off-by: Haren Myneni <haren@us.ibm.com>
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
Diffstat (limited to 'hw/vas.c')
-rw-r--r-- | hw/vas.c | 37 |
1 files changed, 37 insertions, 0 deletions
@@ -6,6 +6,9 @@ #include <phys-map.h> #include <xscom.h> #include <io.h> +#include <xive.h> +#include <interrupts.h> +#include <nvram.h> #include <vas.h> #define vas_err(__fmt,...) prlog(PR_ERR,"VAS: " __fmt, ##__VA_ARGS__) @@ -24,6 +27,7 @@ struct vas { uint64_t xscom_base; uint64_t wcbs; uint32_t vas_irq; + uint64_t vas_port; }; static inline void get_hvwc_mmio_bar(int chipid, uint64_t *start, uint64_t *len) @@ -402,6 +406,12 @@ static void create_mm_dt_node(struct proc_chip *chip) dt_add_property(dn, "ibm,vas-id", &vas->vas_id, sizeof(vas->vas_id)); dt_add_property(dn, "ibm,chip-id", &gcid, sizeof(gcid)); + if (vas->vas_irq) { + dt_add_property_cells(dn, "interrupts", vas->vas_irq, 0); + dt_add_property_cells(dn, "interrupt-parent", + get_ics_phandle()); + dt_add_property_u64(dn, "ibm,vas-port", vas->vas_port); + } } /* @@ -423,6 +433,26 @@ static void disable_vas_inst(struct dt_node *np) reset_north_ctl(chip); } +static void vas_setup_irq(struct proc_chip *chip) +{ + uint64_t port; + uint32_t irq; + + irq = xive_alloc_ipi_irqs(chip->id, 1, 64); + if (irq == XIVE_IRQ_ERROR) { + vas_err("Failed to allocate interrupt sources for chipID %d\n", + chip->id); + return; + } + + vas_vdbg("trigger port: 0x%p\n", xive_get_trigger_port(irq)); + + port = (uint64_t)xive_get_trigger_port(irq); + + chip->vas->vas_irq = irq; + chip->vas->vas_port = port; +} + /* * Initialize one VAS instance and enable it if @enable is true. */ @@ -452,6 +482,13 @@ static int init_vas_inst(struct dt_node *np, bool enable) init_rma(chip)) return -1; + /* + * Use NVRAM 'vas-user-space' config for backward compatibility + * to older kernels. Remove this option in future if not needed. + */ + if (nvram_query_eq_dangerous("vas-user-space", "enable")) + vas_setup_irq(chip); + create_mm_dt_node(chip); prlog(PR_INFO, "VAS: Initialized chip %d\n", chip->id); |