PSI: Fix PSI driven FSP reset sequence

This patch will fix the flow of triggering actual reset of the FSP.

Host should follow the following steps to reset FSP.

1.) Reading the HBC register
2.) Turning on bit 6 and writing the register (fsp reset)
3.) reading the register back
4.) clearing bit  6 and writing the register (clear fsp reset)

Test results:

Initiate HIR  on FSP with the following commands
1) fsptelinit --disablerecovery
2) putmemproc 300000f8 0x00000000deadbeef

Sapphire traces:

SURV: Heartbeat Acknowledgment error from FSP
ELOG: Notified of log 0x50294535 (size: 6356)
FSPLED: FSP_CMD_SET_LED_STATE command received
ELOG: Notified of log 0x50294566 (size: 2708)
FSPLED: FSP_CMD_GET_LED_STATE command received
FSPLED: FSP_CMD_SET_LED_STATE command received
ELOG: Notified of log 0x50294629 (size: 2744)
SURV: [      9be1a4cc2e] Surv ACK timed out; initiating R/R
FSP: fsp_trigger_reset() entry
FSP: Writing reset to DRCR
FSP: DRCR changed, old = 0, new = 8100
SURV: [      9c1f97eccd] Sending the hearbeat command to FSP
FSP: DRCR changed, old = 8100, new = 0
FSP: DRCR ack received. Triggering reset
PSI: Driving FSP reset via PSI
PSI[0x000]: FSP reset start PSIHBCR set to def0300000000000
PSI[0x000]: FSP reset complete. PSIHBCR set to dcf0300000000000
PSI[0x000]: PSI mgmnt interrupt CR=0xdcf09100c0000000
PSI: PSI Reported Error
PSI: PSI Link Inactive Transition
PSI: SEMR set to fff0fff00000
PSI[0x000]: Disabling link!
PSI: PSIHB_CR (error bits) set to 48f0110040000000
PSI: starting link polling
FSP #0: Link down, starting R&R
FSPCON: Closed consoles on account of FSP reset/reload
SURV: Disabling surveillance
FSP: Closing NVRAM on account of FSP Reset
PSI[0x000]: Poll CR=0x48f0100040000000
PSI[0x000]: Poll CR=0x48f0100040000000
PSI[0x000]: Poll CR=0x48f0100040000000
PSI[0x000]: Poll CR=0x48f0100040000000
PSI[0x000]: Poll CR=0x48f0100040000000
...
....
PSI[0x000]: Poll CR=0x48f0100040000000
PSI[0x000]: Poll CR=0x48f0100040000000
PSI[0x000]: Poll CR=0x48f0100040000000
PSI[0x000]: Poll CR=0x48f0100040000000
PSI[0x000]: Poll CR=0xccf0300000000000
PSI[0x000]: Found active link!
PSI: stopping link polling
FSP: Connected to FSP-A
FSP #0: DISR stat change = 0x00000029
FSP #0: DISR stat change = 0x00000201
FSP #0: Detected R&R complete, acking
FSP #0: DISR stat change = 0x00000001
FSP: FSP assuming new role
FSP: Unhandled message ce0900
FSP: SP says Reset/Reload complete
DUMP: FipS dump available. ID = 0x6a000036 [size: 36086215 bytes]
FSP: Reassociating HVSI console 1
FSP: Reassociating HVSI console 2
SURV: Querying FSP's surveillance status
FSP: Reopening NVRAM of FSP Reload complete
FSP NVRAM: Opening nvram...
MDST: Table updated.
FSPCON: Got HMC interface query
SURV: Received heartbeat acknowledge from FSP
FSP: FSP query capabilities

After reset, FSP reached runtime state.

$ smgr mfgState
runtime

On FSP, HIR resgister set to 1 and reset reload is zero.

$ registry -l smgr
smgr/rr_count_hostinitiated:
0001                               [..]

smgr/rr_count_other:
0000                               [..]

Signed-off-by: Mamatha Inamdar <mamatha4@linux.vnet.ibm.com>
Signed-off-by: Ananth N Mavinakayanahalli <ananth@in.ibm.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>

1 files changed, 14 insertions, 4 deletions

diff --git a/hw/psi.c b/hw/psi.c
index 8e46207..eb4eac1 100644
--- a/hw/psi.c
+++ b/hw/psi.c
@@ -53,8 +53,11 @@ void psi_set_link_polling(bool active)
 }
 
 /*
- * Send an encoded reset sequence to the FSP. We should get a PSI interrupt
- * soon after.
+ * Resetting the FSP is a multi step sequence:
+ * 1. Read the PSIHBCR
+ * 2. Set the PSIHBCR[6] -- write register back.
+ * 3. Read PSIHBCR again
+ * 4. Reset PSIHBCR[6] -- write register back.
  */
 void psi_reset_fsp(struct psi *psi)
 {
@@ -66,8 +69,15 @@ void psi_reset_fsp(struct psi *psi)
 		printf("PSI: Driving FSP reset via PSI\n");
 		reg = in_be64(psi->regs + PSIHB_CR);
 		reg &= ~(0xfffull << 20);	/* Reset error bits */
-		reg |= PSIHB_CR_FSP_RESET;	/* Send FSP reset sequence */
-		printf("PSI[0x%03x]: PSIHBCR set to %llx\n",
+		reg |= PSIHB_CR_FSP_RESET;	/* FSP reset trigger start */
+		out_be64(psi->regs + PSIHB_CR, reg);
+		printf("PSI[0x%03x]: FSP reset start PSIHBCR set to %llx\n",
+			psi->chip_id, in_be64(psi->regs + PSIHB_CR));
+
+		reg = in_be64(psi->regs + PSIHB_CR);
+		reg &= ~PSIHB_CR_FSP_RESET;	/* Clear FSP reset bit */
+		out_be64(psi->regs + PSIHB_CR, reg);	/* Complete reset */
+		printf("PSI[0x%03x]: FSP reset complete. PSIHBCR set to %llx\n",
 			psi->chip_id, in_be64(psi->regs + PSIHB_CR));
 	}
 	unlock(&psi_lock);