psi: Workaround for "pulse" external interrupt

The FPGA used on some open power machines generates regular pulses instead
of levels. In that case, reading the status might fail since it's not
latched. In that case, also check the latched event bit in the XIVR.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>

1 files changed, 12 insertions, 0 deletions

diff --git a/hw/psi.c b/hw/psi.c
index eb4eac1..42eac39 100644
--- a/hw/psi.c
+++ b/hw/psi.c
@@ -287,6 +287,18 @@ static void handle_extra_interrupt(struct psi *psi)
 	if (val & PSIHB_IRQ_STAT_HOST_ERR) {
 		if (platform.external_irq)
 			platform.external_irq(psi->chip_id);
+	} else {
+		u64 xivr;
+
+		/*
+		 * The way our FPGA "pulses" the external interrupt
+		 * on BMC machines means we might not see it in the
+		 * status register anymore, so look at the latch in
+		 * the XIVR
+		 */
+		xivr = in_be64(psi->regs + PSIHB_XIVR_HOST_ERR);
+		if (xivr & PPC_BIT(39) && platform.external_irq)
+			platform.external_irq(psi->chip_id);
 	}
 
 	/*