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| author | Russell Currey <ruscur@russell.cc> | 2017-06-09 16:06:04 +1000 |
|---|---|---|
| committer | Stewart Smith <stewart@linux.vnet.ibm.com> | 2017-06-15 13:37:37 +1000 |
| commit | 9953b4d15c4d47b11f9029b1b90f77537af1a715 (patch) | |
| tree | 85ba6f0ab3ed783eb62421612b0d9308abcebd79 /hw/phb4.c | |
| parent | cd48b15b132a5c7ea30ae3fa6f2144236b9ea88b (diff) | |
| download | skiboot-9953b4d15c4d47b11f9029b1b90f77537af1a715.zip skiboot-9953b4d15c4d47b11f9029b1b90f77537af1a715.tar.gz skiboot-9953b4d15c4d47b11f9029b1b90f77537af1a715.tar.bz2 | |
phb4: Mask link down errors during reset
During a hot reset the PCI link will drop, so we need to mask link down
events to prevent unnecessary errors.
Signed-off-by: Russell Currey <ruscur@russell.cc>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
Diffstat (limited to 'hw/phb4.c')
| -rw-r--r-- | hw/phb4.c | 8 |
1 files changed, 8 insertions, 0 deletions
@@ -1818,6 +1818,14 @@ static void phb4_prepare_link_change(struct pci_slot *slot, bool is_up) /* Don't block PCI-CFG */ p->flags &= ~PHB4_CFG_BLOCKED; + /* Clear error link enable & error link down kill enable */ + out_be64(p->regs + PHB_PCIE_MISC_STRAP, 0); + + /* Disable all error status indicators that trigger irqs */ + out_be64(p->regs + PHB_REGB_ERR_INF_ENABLE, 0); + out_be64(p->regs + PHB_REGB_ERR_ERC_ENABLE, 0); + out_be64(p->regs + PHB_REGB_ERR_FAT_ENABLE, 0); + /* * We might lose the bus numbers during the reset operation * and we need to restore them. Otherwise, some adapters (e.g. |