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| author | Michael Neuling <mikey@neuling.org> | 2017-07-12 12:06:48 +1000 |
|---|---|---|
| committer | Stewart Smith <stewart@linux.vnet.ibm.com> | 2017-07-13 10:19:45 +1000 |
| commit | 95f8a8c36a90c31ae9006e8e17d7c26a6b7eb7c9 (patch) | |
| tree | 17bb594c51656a4cae28db455da2c97a54e75471 /hw/phb4.c | |
| parent | 888524d02653bb79707348e13210526dea924985 (diff) | |
| download | skiboot-95f8a8c36a90c31ae9006e8e17d7c26a6b7eb7c9.zip skiboot-95f8a8c36a90c31ae9006e8e17d7c26a6b7eb7c9.tar.gz skiboot-95f8a8c36a90c31ae9006e8e17d7c26a6b7eb7c9.tar.bz2 | |
phb4: Fix order of pfir/nfir clearing in CRESET
According to the workbook, pfir must be cleared before the nfir.
The way we have it now causes the nfir to not clear properly in some
error circumstances.
This swaps the order to match the workbook.
Also updates the comments to be clearer.
Signed-off-by: Michael Neuling <mikey@neuling.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
Diffstat (limited to 'hw/phb4.c')
| -rw-r--r-- | hw/phb4.c | 7 |
1 files changed, 4 insertions, 3 deletions
@@ -2420,7 +2420,7 @@ static int64_t phb4_creset(struct pci_slot *slot) xscom_write(p->chip_id, p->pci_stk_xscom + XPEC_PCI_STK_ETU_RESET, 0x8000000000000000); - /* Clear errors in PFIR and NFIR */ + /* Read errors in PFIR and NFIR */ xscom_read(p->chip_id, p->pci_stk_xscom + 0x0, &p->pfir_cache); xscom_read(p->chip_id, p->pe_stk_xscom + 0x0, &p->nfir_cache); @@ -2433,10 +2433,11 @@ static int64_t phb4_creset(struct pci_slot *slot) if (!(pbcq_status & 0xC000000000000000)) { PHBDBG(p, "CRESET: No pending transactions\n"); - xscom_write(p->chip_id, p->pe_stk_xscom + 0x1, - ~p->nfir_cache); + /* Clear errors in PFIR and NFIR */ xscom_write(p->chip_id, p->pci_stk_xscom + 0x1, ~p->pfir_cache); + xscom_write(p->chip_id, p->pe_stk_xscom + 0x1, + ~p->nfir_cache); /* Clear PHB from reset */ xscom_write(p->chip_id, |