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| author | Oliver O'Halloran <oohall@gmail.com> | 2017-06-15 16:00:22 +1000 |
|---|---|---|
| committer | Stewart Smith <stewart@linux.vnet.ibm.com> | 2017-06-16 14:38:46 +1000 |
| commit | 92d7ccf00bdd6c994341feb013390c28993652bf (patch) | |
| tree | f376330cdff46aca799a7b50c4747634623cf474 /hw/phb4.c | |
| parent | d939c1bbd13cb1f922be80769578eae99a30cad6 (diff) | |
| download | skiboot-92d7ccf00bdd6c994341feb013390c28993652bf.zip skiboot-92d7ccf00bdd6c994341feb013390c28993652bf.tar.gz skiboot-92d7ccf00bdd6c994341feb013390c28993652bf.tar.bz2 | |
hw/phys_map: Use GCIDs as a chip index
Currently we pass in a proc_chip structure to phys_map_get(). All we we
really need from this structure is the Global Chip ID (GCID). This
patch reworks the function so that we only need to pass the GCID which
allows us to use it before the proc_chip structures have been
initialised (i.e in the HDAT parser).
Cc: Michael Neuling <mikey@neuling.org>
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
Acked-By: Michael Neuling <mikey@neuling.org>
Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
Diffstat (limited to 'hw/phb4.c')
| -rw-r--r-- | hw/phb4.c | 10 |
1 files changed, 4 insertions, 6 deletions
@@ -3661,13 +3661,11 @@ static void phb4_probe_stack(struct dt_node *stk_node, uint32_t pec_index, uint64_t mmio_win[4]; unsigned int mmio_win_sz; struct dt_node *np; - struct proc_chip *chip; char *path; uint64_t capp_ucode_base; unsigned int max_link_speed; gcid = dt_get_chip_id(stk_node); - chip = get_chip(gcid); stk_index = dt_prop_get_u32(stk_node, "reg"); phb_num = dt_prop_get_u32(stk_node, "ibm,phb-index"); path = dt_get_path(stk_node); @@ -3686,24 +3684,24 @@ static void phb4_probe_stack(struct dt_node *stk_node, uint32_t pec_index, bar_en = 0; /* Initialize PHB register BAR */ - phys_map_get(chip, PHB4_REG_SPC, phb_num, &phb_bar, NULL); + phys_map_get(gcid, PHB4_REG_SPC, phb_num, &phb_bar, NULL); xscom_write(gcid, nest_stack + XPEC_NEST_STK_PHB_REG_BAR, phb_bar << 8); bar_en |= XPEC_NEST_STK_BAR_EN_PHB; /* Same with INT BAR (ESB) */ - phys_map_get(chip, PHB4_XIVE_ESB, phb_num, &irq_bar, NULL); + phys_map_get(gcid, PHB4_XIVE_ESB, phb_num, &irq_bar, NULL); xscom_write(gcid, nest_stack + XPEC_NEST_STK_IRQ_BAR, irq_bar << 8); bar_en |= XPEC_NEST_STK_BAR_EN_INT; /* Same with MMIO windows */ - phys_map_get(chip, PHB4_64BIT_MMIO, phb_num, &mmio0_bar, &mmio0_sz); + phys_map_get(gcid, PHB4_64BIT_MMIO, phb_num, &mmio0_bar, &mmio0_sz); mmio0_bmask = (~(mmio0_sz - 1)) & 0x00FFFFFFFFFFFFFFULL; xscom_write(gcid, nest_stack + XPEC_NEST_STK_MMIO_BAR0, mmio0_bar << 8); xscom_write(gcid, nest_stack + XPEC_NEST_STK_MMIO_BAR0_MASK, mmio0_bmask << 8); - phys_map_get(chip, PHB4_32BIT_MMIO, phb_num, &mmio1_bar, &mmio1_sz); + phys_map_get(gcid, PHB4_32BIT_MMIO, phb_num, &mmio1_bar, &mmio1_sz); mmio1_bmask = (~(mmio1_sz - 1)) & 0x00FFFFFFFFFFFFFFULL; xscom_write(gcid, nest_stack + XPEC_NEST_STK_MMIO_BAR1, mmio1_bar << 8); xscom_write(gcid, nest_stack + XPEC_NEST_STK_MMIO_BAR1_MASK, mmio1_bmask << 8); |