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| author | Russell Currey <ruscur@russell.cc> | 2017-05-10 17:09:16 +1000 |
|---|---|---|
| committer | Stewart Smith <stewart@linux.vnet.ibm.com> | 2017-05-12 16:19:22 +1000 |
| commit | 85fecf598072cdae850f1eda1f7f2a56882bb68d (patch) | |
| tree | a9a07da6165779256e8cae1c8d14d81a515418ce /hw/phb4.c | |
| parent | 6bc8fda91a4e721c36402c356980bb63c950219e (diff) | |
| download | skiboot-85fecf598072cdae850f1eda1f7f2a56882bb68d.zip skiboot-85fecf598072cdae850f1eda1f7f2a56882bb68d.tar.gz skiboot-85fecf598072cdae850f1eda1f7f2a56882bb68d.tar.bz2 | |
phb4: Add an option for disabling EEH MMIO in nvram
Having the option to disable EEH for MMIO without rebuilding skiboot
could be useful for testing, so check for pci-eeh-mmio=disabled in nvram.
Signed-off-by: Russell Currey <ruscur@russell.cc>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
Diffstat (limited to 'hw/phb4.c')
| -rw-r--r-- | hw/phb4.c | 11 |
1 files changed, 8 insertions, 3 deletions
@@ -55,6 +55,7 @@ #include <xive.h> #include <xscom-p9-regs.h> #include <phys-map.h> +#include <nvram.h> /* Enable this to disable error interrupts for debug purposes */ #define DISABLE_ERR_INTS @@ -2850,9 +2851,13 @@ static void phb4_init_hw(struct phb4 *p, bool first_init) out_be64(p->regs + PHB_PCIE_CRESET, creset); /* Init_16 - PHB Control */ - out_be64(p->regs + PHB_CTRLR, - PHB_CTRLR_IRQ_PGSZ_64K | - SETFIELD(PHB_CTRLR_TVT_ADDR_SEL, 0ull, TVT_2_PER_PE)); + val = PHB_CTRLR_IRQ_PGSZ_64K | + SETFIELD(PHB_CTRLR_TVT_ADDR_SEL, 0ull, TVT_2_PER_PE); + + if (nvram_query_eq("pci-eeh-mmio", "disabled")) + val |= PHB_CTRLR_MMIO_EEH_DISABLE; + + out_be64(p->regs + PHB_CTRLR, val); /* Init_17..40 - Architected IODA3 inits */ phb4_init_ioda3(p); |