pci: Avoid hot resets at boot time

In the PCI post-fundamental reset code, a hot reset is performed at the
end.  This is causing issues at boot time as a reset signal is being sent
downstream before the links are up, which is causing issues on adapters
behind switches.  No errors result in skiboot, but the adapters are not
usable in Linux as a result.

Hot resets also occur in the FSP platform-specific code for conventional
PCI slots, which could cause issues.

This patch fixes some adapters not being configurable in Linux on some
systems.  The issue was not present in skiboot 5.2.x.

Cc: stable # 5.3.x
Signed-off-by: Russell Currey <ruscur@russell.cc>
Acked-by: Gavin Shan <gwshan@linux.vnet.ibm.com>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>

1 files changed, 0 insertions, 8 deletions

diff --git a/hw/phb4.c b/hw/phb4.c
index 385ce8c..efb6a5f 100644
--- a/hw/phb4.c
+++ b/hw/phb4.c
@@ -1951,16 +1951,8 @@ static int64_t phb4_pfreset(struct pci_slot *slot)
 		/* CAPP FPGA requires 1s to flash before polling link */
 		return pci_slot_set_sm_timeout(slot, secs_to_tb(1));
 	case PHB4_SLOT_PFRESET_DEASSERT_DELAY:
-#if 0 	/* PHB3 does a Hreset here. It's unnecessary I think and it's
-	 * causing problems with the simulator croc model so don't do
-	 * it until I figure out Gavin's reasons
-	 */
-		pci_slot_set_state(slot, PHB4_SLOT_HRESET_START);
-		return slot->ops.hreset(slot);
-#else
 		pci_slot_set_state(slot, PHB4_SLOT_LINK_START);
 		return slot->ops.poll_link(slot);
-#endif
 	default:
 		PHBERR(p, "Unexpected slot state %08x\n", slot->state);
 	}