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| author | Benjamin Herrenschmidt <benh@kernel.crashing.org> | 2016-07-07 21:18:47 +1000 |
|---|---|---|
| committer | Stewart Smith <stewart@linux.vnet.ibm.com> | 2016-07-12 20:16:04 +1000 |
| commit | a5011282403ebbc58779eb032c7588aba2e58805 (patch) | |
| tree | f20b59fc11efdb296f66d3071d2e8b04f9a3f10b /hw/phb4.c | |
| parent | 052d7b967ed451d232c02e1cabce8d89ae3266fe (diff) | |
| download | skiboot-a5011282403ebbc58779eb032c7588aba2e58805.zip skiboot-a5011282403ebbc58779eb032c7588aba2e58805.tar.gz skiboot-a5011282403ebbc58779eb032c7588aba2e58805.tar.bz2 | |
interrupts: Use a #interrupt-cells of 2 for XICS interrupts
This is more compliant with PAPR, it will also allow us to
use the second cell for other attributes on P9.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
Diffstat (limited to 'hw/phb4.c')
| -rw-r--r-- | hw/phb4.c | 6 |
1 files changed, 5 insertions, 1 deletions
@@ -2923,11 +2923,15 @@ static void phb4_add_properties(struct phb4 *p) * PCI code based on the content of this structure: */ lsibase = p->base_lsi; - p->phb.lstate.int_size = 1; + p->phb.lstate.int_size = 2; p->phb.lstate.int_val[0][0] = lsibase + PHB4_LSI_PCIE_INTA; + p->phb.lstate.int_val[0][1] = 1; p->phb.lstate.int_val[1][0] = lsibase + PHB4_LSI_PCIE_INTB; + p->phb.lstate.int_val[1][1] = 1; p->phb.lstate.int_val[2][0] = lsibase + PHB4_LSI_PCIE_INTC; + p->phb.lstate.int_val[2][1] = 1; p->phb.lstate.int_val[3][0] = lsibase + PHB4_LSI_PCIE_INTD; + p->phb.lstate.int_val[3][1] = 1; p->phb.lstate.int_parent[0] = icsp; p->phb.lstate.int_parent[1] = icsp; p->phb.lstate.int_parent[2] = icsp; |