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| author | Gavin Shan <gwshan@linux.vnet.ibm.com> | 2015-09-11 14:36:34 +1000 |
|---|---|---|
| committer | Stewart Smith <stewart@linux.vnet.ibm.com> | 2015-09-15 16:15:41 +1000 |
| commit | c34905c558bfd0773da0adf8b7f7d8bedea480a8 (patch) | |
| tree | cdf2ed4aa9a169c7a6fe22c9c71609e363098b01 /hw/p5ioc2-phb.c | |
| parent | ef186c6ce6c9e730a91263aac38153e4257fb354 (diff) | |
| download | skiboot-c34905c558bfd0773da0adf8b7f7d8bedea480a8.zip skiboot-c34905c558bfd0773da0adf8b7f7d8bedea480a8.tar.gz skiboot-c34905c558bfd0773da0adf8b7f7d8bedea480a8.tar.bz2 | |
PCI: Clear error bits after changing MPS
Chaning MPS on PCI upstream bridge might cause error bits set on
downstream endpoints when system boots into Linux as below case
shows:
host# lspci -vvs 0001:06:00.0
0001:06:00.0 Ethernet controller: Broadcom Corporation \
NetXtreme II BCM57810 10 Gigabit Ethernet (rev 10)
:
DevSta: CorrErr+ UncorrErr- FatalErr- UnsuppReq+ AuxPwr- TransPend-
:
CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+
This clears those error bits in AER and PCIe capability after MPS
is changed. With the patch applied, no more error bits are seen.
Reported-by: John Walthour <jwalthour@us.ibm.com>
Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
Diffstat (limited to 'hw/p5ioc2-phb.c')
0 files changed, 0 insertions, 0 deletions