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| author | Dan Streetman <ddstreet@ieee.org> | 2015-03-27 00:40:29 -0400 |
|---|---|---|
| committer | Stewart Smith <stewart@linux.vnet.ibm.com> | 2015-03-31 15:42:37 +1100 |
| commit | 3a340edbc9cc8428c48def84ffa183343f629748 (patch) | |
| tree | 44fd25bec175cdf611106d2da979f7375af5f141 /hw/nx-crypto.c | |
| parent | 555c076c632f50eab5c21a37b939a970fcdf7efe (diff) | |
| download | skiboot-3a340edbc9cc8428c48def84ffa183343f629748.zip skiboot-3a340edbc9cc8428c48def84ffa183343f629748.tar.gz skiboot-3a340edbc9cc8428c48def84ffa183343f629748.tar.bz2 | |
set NX crb input queues to 842 only
Set the NX crb input queues to be used by 842 only, by not reserving any input
queue slots for the sym or asym engines. This allows the maximum number of
842 crb requests to be queued up, to (hopefully) improve 842 performance.
This patch isn't critical, as the default is no extra input queue locations
for asym, and only 1 extra input queue location for sym, so this only takes
sym's extra location for use by 842.
There is 1 each dedicated input queue location for asym and sym (and 842), so
this patch won't prevent them from working if support is ever added for them.
Signed-off-by: Dan Streetman <ddstreet@ieee.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
Diffstat (limited to 'hw/nx-crypto.c')
| -rw-r--r-- | hw/nx-crypto.c | 32 |
1 files changed, 31 insertions, 1 deletions
diff --git a/hw/nx-crypto.c b/hw/nx-crypto.c index 9d15e87..6558db0 100644 --- a/hw/nx-crypto.c +++ b/hw/nx-crypto.c @@ -25,6 +25,8 @@ #define CFG_SYM_ENABLE (0) /* disable sym engines */ #define CFG_ASYM_FC_ENABLE (0) /* disable all asym functions */ #define CFG_ASYM_ENABLE (0) /* disable asym engines */ +#define CFG_CRB_IQ_SYM (0) /* don't use any extra input queues */ +#define CFG_CRB_IQ_ASYM (0) /* don't use any extra input queues */ #define AES_SHA_MAX_RR (1) /* valid range: 1-8 */ #define AES_SHA_CSB_WR NX_DMA_CSB_WR_PDMA #define AES_SHA_COMPLETION_MODE NX_DMA_COMPLETION_MODE_PDMA @@ -206,6 +208,28 @@ static int nx_cfg_dma(u32 gcid, u64 xcfg) return rc; } +static int nx_cfg_iq(u32 gcid, u64 xcfg) +{ + u64 cfg; + int rc; + + rc = xscom_read(gcid, xcfg, &cfg); + if (rc) + return rc; + + cfg = SETFIELD(NX_CRB_IQ_SYM, cfg, CFG_CRB_IQ_SYM); + cfg = SETFIELD(NX_CRB_IQ_ASYM, cfg, CFG_CRB_IQ_ASYM); + + rc = xscom_write(gcid, xcfg, cfg); + if (rc) + prerror("NX%d: ERROR: CRB Input Queue failure %d\n", gcid, rc); + else + prlog(PR_DEBUG, "NX%d: CRB Input Queue 0x%016lx\n", + gcid, (unsigned long)cfg); + + return rc; +} + static int nx_cfg_ee(u32 gcid, u64 xcfg) { u64 cfg; @@ -236,7 +260,7 @@ void nx_create_crypto_node(struct dt_node *node) { u32 gcid; u32 pb_base; - u64 cfg_dma, cfg_sym, cfg_asym, cfg_ee; + u64 cfg_dma, cfg_sym, cfg_asym, cfg_iq, cfg_ee; int rc; gcid = dt_get_chip_id(node); @@ -248,11 +272,13 @@ void nx_create_crypto_node(struct dt_node *node) cfg_dma = pb_base + NX_P7_DMA_CFG; cfg_sym = pb_base + NX_P7_SYM_CFG; cfg_asym = pb_base + NX_P7_ASYM_CFG; + cfg_iq = pb_base + NX_P7_CRB_IQ; cfg_ee = pb_base + NX_P7_EE_CFG; } else if (dt_node_is_compatible(node, "ibm,power8-nx")) { cfg_dma = pb_base + NX_P8_DMA_CFG; cfg_sym = pb_base + NX_P8_SYM_CFG; cfg_asym = pb_base + NX_P8_ASYM_CFG; + cfg_iq = pb_base + NX_P8_CRB_IQ; cfg_ee = pb_base + NX_P8_EE_CFG; } else { prerror("NX%d: ERROR: Unknown NX type!\n", gcid); @@ -271,6 +297,10 @@ void nx_create_crypto_node(struct dt_node *node) if (rc) return; + rc = nx_cfg_iq(gcid, cfg_iq); + if (rc) + return; + rc = nx_cfg_ee(gcid, cfg_ee); if (rc) return; |