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authorMichael Neuling <mikey@neuling.org>2017-11-14 22:23:03 +1100
committerStewart Smith <stewart@linux.vnet.ibm.com>2017-11-15 02:29:38 -0600
commit2dbbcddb43b7f14b879c5ab45d9d6abef8763922 (patch)
tree3bec0c950a606478c95a698c937c35292a946ff3 /hw/npu2.c
parent0a3df98b0a7ed3c4b61755fd26ab48c804a7c041 (diff)
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npu2: Refactor BAR setting code
This refactors the BAR setting code to make it clearer and handle a larger range of BAR addresses. This is needed as we are about to move the GPU to a physical address that is currently not supported by this code. This change derives group and chip sections of the BAR from the base address rather than the chip_id now. mem sel is also derived from the base address, rather than assuming 0. No functional change. Signed-off-by: Michael Neuling <mikey@neuling.org> Reviewed-by: Balbir Singh <bsingharora@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com> (cherry picked from commit 3c0408ded5a14e110c8a418be305ac20714cb32d) Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
Diffstat (limited to 'hw/npu2.c')
-rw-r--r--hw/npu2.c11
1 files changed, 6 insertions, 5 deletions
diff --git a/hw/npu2.c b/hw/npu2.c
index 889acd2..5d9e0a0 100644
--- a/hw/npu2.c
+++ b/hw/npu2.c
@@ -649,11 +649,12 @@ static int npu2_assign_gmb(struct npu2_dev *ndev)
npu2_get_gpu_base(ndev, &base, &size);
- /* Base address is in GB */
- base >>= 30;
- val = SETFIELD(NPU2_MEM_BAR_SEL_MEM, 0ULL, 4);
- val = SETFIELD(NPU2_MEM_BAR_NODE_ADDR, val, base);
- val = SETFIELD(NPU2_MEM_BAR_GROUP | NPU2_MEM_BAR_CHIP, val, p->chip_id);
+ NPU2DBG(p, "Setting BAR region dt:%llx\n", base);
+ val = SETFIELD(NPU2_MEM_BAR_EN, 0ULL, 1);
+ val = SETFIELD(NPU2_MEM_BAR_SEL_MEM, val, base >> (63-14));
+ val = SETFIELD(NPU2_MEM_BAR_GROUP, val, base >> (63-18));
+ val = SETFIELD(NPU2_MEM_BAR_CHIP, val, base >> (63-21));
+ val = SETFIELD(NPU2_MEM_BAR_NODE_ADDR, val, base >> (63-33));
val = SETFIELD(NPU2_MEM_BAR_POISON, val, 1);
val = SETFIELD(NPU2_MEM_BAR_GRANULE, val, 0);