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| author | Reza Arbab <arbab@linux.ibm.com> | 2019-01-09 09:58:45 -0600 |
|---|---|---|
| committer | Stewart Smith <stewart@linux.ibm.com> | 2019-01-16 00:46:49 -0600 |
| commit | 69ca8a8ff7a96ddb0f2bd9cdc54f69c364289ae6 (patch) | |
| tree | ed3c57b7790e09e8ffec0f9c48fc2fac2a669542 /hw/npu2.c | |
| parent | 552cb9e371d82cea05ce5e6a2b8ae033361e2c72 (diff) | |
| download | skiboot-69ca8a8ff7a96ddb0f2bd9cdc54f69c364289ae6.zip skiboot-69ca8a8ff7a96ddb0f2bd9cdc54f69c364289ae6.tar.gz skiboot-69ca8a8ff7a96ddb0f2bd9cdc54f69c364289ae6.tar.bz2 | |
npu2: Remove unused npu2::bdf2pe_cache
This cache is written but never read. Wiring it up would gain us little
(except added complexity), and it obviously hasn't been missed thus far,
so remove it altogether.
Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com>
Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
Diffstat (limited to 'hw/npu2.c')
| -rw-r--r-- | hw/npu2.c | 30 |
1 files changed, 0 insertions, 30 deletions
@@ -883,35 +883,6 @@ static void npu2_phb_final_fixup(struct phb *phb) static void npu2_init_ioda_cache(struct npu2 *p) { - uint64_t val[2]; - uint32_t i; - - /* - * PE mapping: there are two sets of registers. One of them - * is used to map PEs for transactions. Another set is used - * for error routing. We should have consistent setting in - * both of them. Note that each brick can support 3 PEs at - * the maximal degree. For now, we just support one PE per - * brick. - */ - val[0] = NPU2_CQ_BRICK_BDF2PE_MAP_ENABLE; - val[0] = SETFIELD(NPU2_CQ_BRICK_BDF2PE_MAP_PE, - val[0], NPU2_RESERVED_PE_NUM); - val[1] = NPU2_MISC_BRICK_BDF2PE_MAP_ENABLE; - val[1] = SETFIELD(NPU2_MISC_BRICK_BDF2PE_MAP_PE, - val[1], NPU2_RESERVED_PE_NUM); - for (i = 0; i < ARRAY_SIZE(p->bdf2pe_cache); i++) { - if (i < ARRAY_SIZE(p->bdf2pe_cache)) - p->bdf2pe_cache[i] = SETFIELD(NPU2_CQ_BRICK_BDF2PE_MAP_BDF, - val[0], i / 3); - else - p->bdf2pe_cache[i] = SETFIELD(NPU2_MISC_BRICK_BDF2PE_MAP_BDF, - val[1], i / 3); - - if (i % 3) - p->bdf2pe_cache[i] = 0ul; - } - /* TVT */ memset(p->tve_cache, 0, sizeof(p->tve_cache)); } @@ -1220,7 +1191,6 @@ static int64_t npu2_set_pe(struct phb *phb, val = SETFIELD(NPU2_MISC_BRICK_BDF2PE_MAP_BDF, val, dev->nvlink.gpu_bdfn); reg = NPU2_REG_OFFSET(NPU2_STACK_MISC, NPU2_BLOCK_MISC, NPU2_MISC_BRICK0_BDF2PE_MAP0 + (dev->brick_index * 0x18)); - p->bdf2pe_cache[dev->brick_index] = val; npu2_write(p, reg, val); return OPAL_SUCCESS; |