diff options
| author | Reza Arbab <arbab@linux.vnet.ibm.com> | 2017-08-30 17:38:27 -0500 |
|---|---|---|
| committer | Stewart Smith <stewart@linux.vnet.ibm.com> | 2017-09-04 20:45:35 -0500 |
| commit | 7af2a68d1ac7906bbf3a098c82337d563d2a801d (patch) | |
| tree | 17c066d26df40a4f0555ae46a58289e463576ece /hw/npu2-hw-procedures.c | |
| parent | 4f9c620f477860db7602ff5b9dfaf83ca0dd1b18 (diff) | |
| download | skiboot-7af2a68d1ac7906bbf3a098c82337d563d2a801d.zip skiboot-7af2a68d1ac7906bbf3a098c82337d563d2a801d.tar.gz skiboot-7af2a68d1ac7906bbf3a098c82337d563d2a801d.tar.bz2 | |
npu2: hw-procedures: Update PHY DC calibration procedure
Per the updated programming guide (procedure 1.2.4), set
rx_pr_edge_track_cntl and rx_pr_fw_off appropriately before and after
calibration.
Signed-off-by: Reza Arbab <arbab@linux.vnet.ibm.com>
Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
Diffstat (limited to 'hw/npu2-hw-procedures.c')
| -rw-r--r-- | hw/npu2-hw-procedures.c | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/hw/npu2-hw-procedures.c b/hw/npu2-hw-procedures.c index 5ccc1a0..a140aed 100644 --- a/hw/npu2-hw-procedures.c +++ b/hw/npu2-hw-procedures.c @@ -59,6 +59,8 @@ struct npu2_phy_reg NPU2_PHY_TX_UNLOAD_CLK_DISABLE = {0x103, 56, 1}; struct npu2_phy_reg NPU2_PHY_TX_FIFO_INIT = {0x105, 53, 1}; struct npu2_phy_reg NPU2_PHY_TX_RXCAL = {0x103, 57, 1}; struct npu2_phy_reg NPU2_PHY_RX_INIT_DONE = {0x0ca, 48, 1}; +struct npu2_phy_reg NPU2_PHY_RX_PR_EDGE_TRACK_CNTL = {0x092, 48, 2}; +struct npu2_phy_reg NPU2_PHY_RX_PR_FW_OFF = {0x08a, 56, 1}; /* These registers are per-PHY, not per lane */ struct npu2_phy_reg NPU2_PHY_TX_ZCAL_SWO_EN = {0x3c9, 48, 1}; @@ -521,6 +523,9 @@ static uint32_t phy_rx_dccal(struct npu2_dev *ndev) int lane; FOR_EACH_LANE(ndev, lane) + phy_write_lane(ndev, &NPU2_PHY_RX_PR_FW_OFF, lane, 1); + + FOR_EACH_LANE(ndev, lane) phy_write_lane(ndev, &NPU2_PHY_RX_RUN_DCCAL, lane, 1); return PROCEDURE_NEXT; @@ -537,8 +542,11 @@ static uint32_t phy_rx_dccal_complete(struct npu2_dev *ndev) FOR_EACH_LANE(ndev, lane) phy_write_lane(ndev, &NPU2_PHY_RX_RUN_DCCAL, lane, 0); - FOR_EACH_LANE(ndev, lane) + FOR_EACH_LANE(ndev, lane) { phy_write_lane(ndev, &NPU2_PHY_RX_B_BANK_CONTROLS, lane, 0); + phy_write_lane(ndev, &NPU2_PHY_RX_PR_EDGE_TRACK_CNTL, lane, 0); + phy_write_lane(ndev, &NPU2_PHY_RX_PR_FW_OFF, lane, 0); + } return PROCEDURE_NEXT; } |