diff options
| author | Alistair Popple <alistair@popple.id.au> | 2017-08-18 14:11:17 +1000 |
|---|---|---|
| committer | Stewart Smith <stewart@linux.vnet.ibm.com> | 2017-08-27 19:34:33 -0500 |
| commit | 2d4dd7b19ede9aa62c88ead20f97f3e51eb18984 (patch) | |
| tree | 992fbb381ecef47d4a8b6460b3409f17cc7682fa /hw/npu2-hw-procedures.c | |
| parent | 201fd50f208d680cfb19c0e508ca46b4f9cc75dc (diff) | |
| download | skiboot-2d4dd7b19ede9aa62c88ead20f97f3e51eb18984.zip skiboot-2d4dd7b19ede9aa62c88ead20f97f3e51eb18984.tar.gz skiboot-2d4dd7b19ede9aa62c88ead20f97f3e51eb18984.tar.bz2 | |
hw/npu2-hw-procedures.c: Update PHY_RESET procedure
Newer versions of Hostboot will have various clocks powered down by default
to save power. Therefore we need to power them up before accessing the OBUS
PHY.
Signed-off-by: Alistair Popple <alistair@popple.id.au>
Reviewed-by: Reza Arbab <arbab@linux.vnet.ibm.com>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
Diffstat (limited to 'hw/npu2-hw-procedures.c')
| -rw-r--r-- | hw/npu2-hw-procedures.c | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/hw/npu2-hw-procedures.c b/hw/npu2-hw-procedures.c index de70009..c9e7673 100644 --- a/hw/npu2-hw-procedures.c +++ b/hw/npu2-hw-procedures.c @@ -87,6 +87,11 @@ struct npu2_phy_reg NPU2_PHY_RX_HIST_MIN_EYE_WIDTH = {0x24e, 54, 8}; struct npu2_phy_reg NPU2_PHY_RX_HIST_MIN_EYE_WIDTH_LANE = {0x24e, 49, 5}; struct npu2_phy_reg NPU2_PHY_RX_HIST_MIN_EYE_WIDTH_VALID= {0x24e, 48, 1}; +struct npu2_phy_reg NPU2_PHY_RX_CLKDIST_PDWN = {0x204, 48, 3}; +struct npu2_phy_reg NPU2_PHY_RX_IREF_PDWN = {0x230, 54, 1}; +struct npu2_phy_reg NPU2_PHY_TX_CLKDIST_PDWN = {0x305, 48, 3}; +struct npu2_phy_reg NPU2_PHY_RX_CTL_DATASM_CLKDIST_PDWN = {0x2e0, 60, 1}; + #define NPU2_PHY_REG(scom_base, reg, lane) \ SETFIELD(PPC_BITMASK(27, 31), ((reg)->offset << 42) | scom_base, lane) @@ -252,6 +257,12 @@ static uint32_t phy_reset(struct npu2_dev *ndev) { int lane; + /* Power on clocks */ + phy_write(ndev, &NPU2_PHY_RX_CLKDIST_PDWN, 0); + phy_write(ndev, &NPU2_PHY_RX_IREF_PDWN, 1); + phy_write(ndev, &NPU2_PHY_TX_CLKDIST_PDWN, 0); + phy_write(ndev, &NPU2_PHY_RX_CTL_DATASM_CLKDIST_PDWN, 0); + FOR_EACH_LANE(ndev, lane) phy_write_lane(ndev, &NPU2_PHY_RX_RUN_LANE, lane, 0); |