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author | Andrew Donnellan <andrew.donnellan@au1.ibm.com> | 2018-03-01 18:57:10 +1100 |
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committer | Stewart Smith <stewart@linux.vnet.ibm.com> | 2018-03-01 20:17:54 -0600 |
commit | 399151e1425e496dad5fb47940dafdd562f255aa (patch) | |
tree | 02514599b66d5048c63a377715415ba162bb1213 /hw/npu2-common.c | |
parent | fa1eeea2e98728d364f0bae706d06905cc46ee5c (diff) | |
download | skiboot-399151e1425e496dad5fb47940dafdd562f255aa.zip skiboot-399151e1425e496dad5fb47940dafdd562f255aa.tar.gz skiboot-399151e1425e496dad5fb47940dafdd562f255aa.tar.bz2 |
npu2: Split out common helper functions into separate file
Split out common helper functions for NPU register access into a separate
file, as these will be used extensively by both NVLink and OpenCAPI code.
Signed-off-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com>
Acked-by: Reza Arbab <arbab@linux.vnet.ibm.com>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
Diffstat (limited to 'hw/npu2-common.c')
-rw-r--r-- | hw/npu2-common.c | 114 |
1 files changed, 114 insertions, 0 deletions
diff --git a/hw/npu2-common.c b/hw/npu2-common.c new file mode 100644 index 0000000..0c22d61 --- /dev/null +++ b/hw/npu2-common.c @@ -0,0 +1,114 @@ +/* Copyright 2013-2018 IBM Corp. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + * implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include <skiboot.h> +#include <xscom.h> +#include <pci.h> +#include <npu2.h> +#include <npu2-regs.h> +#include <bitutils.h> + +bool is_p9dd1(void) +{ + struct proc_chip *chip = next_chip(NULL); + + return chip && + (chip->type == PROC_CHIP_P9_NIMBUS || + chip->type == PROC_CHIP_P9_CUMULUS) && + (chip->ec_level & 0xf0) == 0x10; +} + +/* + * We use the indirect method because it uses the same addresses as + * the MMIO offsets (NPU RING) + */ +static void npu2_scom_set_addr(uint64_t gcid, uint64_t scom_base, + uint64_t addr, uint64_t size) +{ + uint64_t isa = is_p9dd1() ? NPU2_DD1_MISC_SCOM_IND_SCOM_ADDR : + NPU2_MISC_SCOM_IND_SCOM_ADDR; + + addr = SETFIELD(NPU2_MISC_DA_ADDR, 0ull, addr); + addr = SETFIELD(NPU2_MISC_DA_LEN, addr, size); + xscom_write(gcid, scom_base + isa, addr); +} + +void npu2_scom_write(uint64_t gcid, uint64_t scom_base, + uint64_t reg, uint64_t size, + uint64_t val) +{ + uint64_t isd = is_p9dd1() ? NPU2_DD1_MISC_SCOM_IND_SCOM_DATA : + NPU2_MISC_SCOM_IND_SCOM_DATA; + + npu2_scom_set_addr(gcid, scom_base, reg, size); + xscom_write(gcid, scom_base + isd, val); +} + +uint64_t npu2_scom_read(uint64_t gcid, uint64_t scom_base, + uint64_t reg, uint64_t size) +{ + uint64_t val; + uint64_t isd = is_p9dd1() ? NPU2_DD1_MISC_SCOM_IND_SCOM_DATA : + NPU2_MISC_SCOM_IND_SCOM_DATA; + + npu2_scom_set_addr(gcid, scom_base, reg, size); + xscom_read(gcid, scom_base + isd, &val); + + return val; +} + +void npu2_write_4b(struct npu2 *p, uint64_t reg, uint32_t val) +{ + npu2_scom_write(p->chip_id, p->xscom_base, reg, NPU2_MISC_DA_LEN_4B, + (uint64_t)val << 32); +} + +uint32_t npu2_read_4b(struct npu2 *p, uint64_t reg) +{ + return npu2_scom_read(p->chip_id, p->xscom_base, reg, + NPU2_MISC_DA_LEN_4B) >> 32; +} + +void npu2_write(struct npu2 *p, uint64_t reg, uint64_t val) +{ + npu2_scom_write(p->chip_id, p->xscom_base, reg, NPU2_MISC_DA_LEN_8B, val); +} + +uint64_t npu2_read(struct npu2 *p, uint64_t reg) +{ + return npu2_scom_read(p->chip_id, p->xscom_base, reg, NPU2_MISC_DA_LEN_8B); +} + +void npu2_write_mask(struct npu2 *p, uint64_t reg, uint64_t val, uint64_t mask) +{ + uint64_t new_val; + + new_val = npu2_read(p, reg); + new_val &= ~mask; + new_val |= val & mask; + npu2_scom_write(p->chip_id, p->xscom_base, reg, NPU2_MISC_DA_LEN_8B, new_val); +} + +void npu2_write_mask_4b(struct npu2 *p, uint64_t reg, uint32_t val, uint32_t mask) +{ + uint32_t new_val; + + new_val = npu2_read_4b(p, reg); + new_val &= ~mask; + new_val |= val & mask; + npu2_scom_write(p->chip_id, p->xscom_base, reg, NPU2_MISC_DA_LEN_4B, + (uint64_t)new_val << 32); +} |