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| author | Christophe Lombard <clombard@linux.vnet.ibm.com> | 2021-10-14 17:57:02 +0200 |
|---|---|---|
| committer | Vasant Hegde <hegdevasant@linux.vnet.ibm.com> | 2021-10-19 12:26:01 +0530 |
| commit | d5b79b2e9bb63ec18b5b5e4d027d5d1d1b0a4e28 (patch) | |
| tree | 1f88a34106d1a9c1c238588ebc3f90e4b4f74b5d /hw/npu-opal.c | |
| parent | e89e5b9b76923ac284bb68c3083e4bd1524e450b (diff) | |
| download | skiboot-d5b79b2e9bb63ec18b5b5e4d027d5d1d1b0a4e28.zip skiboot-d5b79b2e9bb63ec18b5b5e4d027d5d1d1b0a4e28.tar.gz skiboot-d5b79b2e9bb63ec18b5b5e4d027d5d1d1b0a4e28.tar.bz2 | |
pau: update current opal call functions
Update the content of three current OPAL API calls to support PAU.
- OPAL_NPU_SPA_SETUP
The Shared Process Area (SPA) is a table containing one entry (a
"Process Element") per memory context which can be accessed by the
OpenCAPI device.
- OPAL_NPU_SPA_CLEAR_CACHE
The PAU keeps a cache of recently accessed memory contexts. When a
Process Element is removed from the SPA, the cache for the link must
be cleared.
- OPAL_NPU_TL_SET
The Transaction Layer specification defines several templates for
messages to be exchanged on the link. During link setup, the host
and device must negotiate what templates are supported on both sides
and at what rates those messages can be sent.
Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com>
Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
Diffstat (limited to 'hw/npu-opal.c')
| -rw-r--r-- | hw/npu-opal.c | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/hw/npu-opal.c b/hw/npu-opal.c index 73158b1..cf13690 100644 --- a/hw/npu-opal.c +++ b/hw/npu-opal.c @@ -7,6 +7,7 @@ #include <pci.h> #include <phb4.h> #include <npu2.h> +#include <pau.h> #define TL_RATE_BUF_SIZE 32 @@ -184,6 +185,9 @@ static int64_t opal_npu_spa_setup(uint64_t phb_id, uint32_t bdfn, if (phb->phb_type == phb_type_npu_v2_opencapi) return npu2_opencapi_spa_setup(phb, bdfn, addr, PE_mask); + if (phb->phb_type == phb_type_pau_opencapi) + return pau_opencapi_spa_setup(phb, bdfn, addr, PE_mask); + return OPAL_PARAMETER; } opal_call(OPAL_NPU_SPA_SETUP, opal_npu_spa_setup, 4); @@ -202,6 +206,9 @@ static int64_t opal_npu_spa_clear_cache(uint64_t phb_id, uint32_t bdfn, if (phb->phb_type == phb_type_npu_v2_opencapi) return npu2_opencapi_spa_clear_cache(phb, bdfn, PE_handle); + if (phb->phb_type == phb_type_pau_opencapi) + return pau_opencapi_spa_clear_cache(phb, bdfn, PE_handle); + return OPAL_PARAMETER; } opal_call(OPAL_NPU_SPA_CLEAR_CACHE, opal_npu_spa_clear_cache, 3); @@ -222,6 +229,10 @@ static int64_t opal_npu_tl_set(uint64_t phb_id, uint32_t bdfn, return npu2_opencapi_tl_set(phb, bdfn, capabilities, rate); + if (phb->phb_type == phb_type_pau_opencapi) + return pau_opencapi_tl_set(phb, bdfn, capabilities, + rate); + return OPAL_PARAMETER; } opal_call(OPAL_NPU_TL_SET, opal_npu_tl_set, 5); |