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| author | Russell Currey <ruscur@russell.cc> | 2016-01-07 14:36:28 +1100 |
|---|---|---|
| committer | Stewart Smith <stewart@linux.vnet.ibm.com> | 2016-01-15 15:04:57 +1100 |
| commit | b25529d182b53be0b760638c812c422b794546e4 (patch) | |
| tree | 160544826a3be00936d01c55c732f8f023fe589a /hw/npu-hw-procedures.c | |
| parent | 2e4cc4dca8c0d31138adc52076b38d80c5a6bef0 (diff) | |
| download | skiboot-b25529d182b53be0b760638c812c422b794546e4.zip skiboot-b25529d182b53be0b760638c812c422b794546e4.tar.gz skiboot-b25529d182b53be0b760638c812c422b794546e4.tar.bz2 | |
nvlink: Use SCOMs instead of MMIO in reset procedure
EEH in the kernel shuts down MMIO BARs as part of freeze recovery.
This can cause the reset procedure, which you probably want to work
during a freeze, to fail because it can't do operations with MMIO.
Refactor the MMIO operations to use SCOM instead.
Signed-off-by: Russell Currey <ruscur@russell.cc>
Acked-By: Alistair Popple <alistair@popple.id.au>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
Diffstat (limited to 'hw/npu-hw-procedures.c')
| -rw-r--r-- | hw/npu-hw-procedures.c | 16 |
1 files changed, 7 insertions, 9 deletions
diff --git a/hw/npu-hw-procedures.c b/hw/npu-hw-procedures.c index 118ed6d..24f3b2c 100644 --- a/hw/npu-hw-procedures.c +++ b/hw/npu-hw-procedures.c @@ -132,13 +132,12 @@ DEFINE_PROCEDURE(nop); * incorporates AT reset. */ static uint32_t reset_npu_dl(struct npu_dev *npu_dev) { - void *ntl_base = (void *) npu_dev->bar.base; uint64_t val; /* Assert NPU reset */ - val = in_be64(ntl_base + NTL_CONTROL); + xscom_read(npu_dev->npu->chip_id, npu_dev->xscom + NX_NTL_CONTROL, &val); val |= NTL_CONTROL_RESET; - out_be64(ntl_base + NTL_CONTROL, val); + xscom_write(npu_dev->npu->chip_id, npu_dev->xscom + NX_NTL_CONTROL, val); /* Put the Nvidia logic in reset */ dl_write(npu_dev, NDL_CONTROL, 0xe8000000); @@ -148,14 +147,13 @@ static uint32_t reset_npu_dl(struct npu_dev *npu_dev) /* Release NPU from reset */ val &= ~NTL_CONTROL_RESET; - out_be64(ntl_base + NTL_CONTROL, val); + xscom_write(npu_dev->npu->chip_id, npu_dev->xscom + NX_NTL_CONTROL, val); /* Setup up TL credits */ - out_be64(ntl_base + TL_CMD_CR, PPC_BIT(0)); - out_be64(ntl_base + TL_CMD_D_CR, PPC_BIT(0)); - out_be64(ntl_base + TL_RSP_CR, PPC_BIT(15)); - out_be64(ntl_base + TL_RSP_D_CR, PPC_BIT(15)); - + xscom_write(npu_dev->npu->chip_id, npu_dev->xscom + NX_TL_CMD_CR, PPC_BIT(0)); + xscom_write(npu_dev->npu->chip_id, npu_dev->xscom + NX_TL_CMD_D_CR, PPC_BIT(0)); + xscom_write(npu_dev->npu->chip_id, npu_dev->xscom + NX_TL_RSP_CR, PPC_BIT(15)); + xscom_write(npu_dev->npu->chip_id, npu_dev->xscom + NX_TL_RSP_D_CR, PPC_BIT(15)); return PROCEDURE_COMPLETE; } DEFINE_PROCEDURE(reset_npu_dl); |