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| author | Oliver O'Halloran <oohall@gmail.com> | 2017-11-27 15:49:04 +1100 |
|---|---|---|
| committer | Stewart Smith <stewart@linux.vnet.ibm.com> | 2017-11-28 20:39:07 -0600 |
| commit | 7fb517898f69ea008077297617e1035827e29417 (patch) | |
| tree | e1f2919b262da169b607ed41b77ebcb5f4df40a5 /hw/lpc.c | |
| parent | 0dde9cd5d22b8cdb97d55b2ff5f65f5343643666 (diff) | |
| download | skiboot-7fb517898f69ea008077297617e1035827e29417.zip skiboot-7fb517898f69ea008077297617e1035827e29417.tar.gz skiboot-7fb517898f69ea008077297617e1035827e29417.tar.bz2 | |
lpc: Clear pending IRQs at boot
When we come in from hostboot the LPC master has the bus reset indicator
set. This error isn't handled until the host kernel unmasks interrupts,
at which point we get the following suprious error:
[ 20.053560375,3] LPC: Got LPC reset on chip 0x0 !
[ 20.053564560,3] LPC[000]: Unknown LPC error Error address reg: 0x00000000
Fix this by clearing the various error bits in the LPC status register
before we initalise the skiboot LPC bus driver.
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
Diffstat (limited to 'hw/lpc.c')
| -rw-r--r-- | hw/lpc.c | 4 |
1 files changed, 4 insertions, 0 deletions
@@ -1176,6 +1176,10 @@ static void lpc_init_chip_p9(struct dt_node *opb_node) /* Mask all interrupts for now */ opb_write(lpc, lpc_reg_opb_base + LPC_HC_IRQMASK, 0, 4); + /* Clear any stale LPC bus errors */ + opb_write(lpc, lpc_reg_opb_base + LPC_HC_IRQSTAT, + LPC_HC_IRQ_BASE_IRQS, 4); + /* Default with routing to PSI SerIRQ 0, this will be updated * later when interrupts are initialized. */ |