diff options
author | Anju T Sudhakar <anju@linux.vnet.ibm.com> | 2021-08-04 12:51:04 +0530 |
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committer | Vasant Hegde <hegdevasant@linux.vnet.ibm.com> | 2021-08-06 12:23:59 +0530 |
commit | eb9047292b0d3604ed31c09e8d0501615c8ce8a8 (patch) | |
tree | c67443341fb3305d7bd03e881b1626aeccd66d8e /hw/imc.c | |
parent | 8e5d736cb87ff7577df8b8008bf364693f48b614 (diff) | |
download | skiboot-eb9047292b0d3604ed31c09e8d0501615c8ce8a8.zip skiboot-eb9047292b0d3604ed31c09e8d0501615c8ce8a8.tar.gz skiboot-eb9047292b0d3604ed31c09e8d0501615c8ce8a8.tar.bz2 |
hw/imc: Power10 support
POWER10 IMC support:
Add POWER10 scom addresses for IMC
Add support for IMC trace-mode
Fix the catalog subit for POWER10
Signed-off-by: Anju T Sudhakar <anju@linux.vnet.ibm.com>
Signed-off-by: Madhavan Srinivasan <maddy@linux.ibm.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
Diffstat (limited to 'hw/imc.c')
-rw-r--r-- | hw/imc.c | 61 |
1 files changed, 51 insertions, 10 deletions
@@ -170,6 +170,20 @@ static unsigned int htm_scom_index_p9[] = { 0x10012700 }; +static unsigned int pdbar_scom_index_p10[] = { + 0x2001868B, + 0x2001468B, + 0x2001268B, + 0x2001168B +}; + +static unsigned int htm_scom_index_p10[] = { + 0x20018680, + 0x20014680, + 0x20012680, + 0x20011680 +}; + static struct imc_chip_cb *get_imc_cb(uint32_t chip_id) { struct proc_chip *chip = get_chip(chip_id); @@ -263,13 +277,23 @@ static bool is_imc_device_type_supported(struct dt_node *node) if (val == IMC_COUNTER_TRACE) { pvr = mfspr(SPR_PVR); - /* - * Trace mode is supported in Nimbus DD2.2 - * and later versions. - */ - if ((chip->type == PROC_CHIP_P9_NIMBUS) && - (PVR_VERS_MAJ(pvr) == 2) && (PVR_VERS_MIN(pvr) >= 2)) + + switch (chip->type) { + case PROC_CHIP_P9_NIMBUS: + /* + * Trace mode is supported in Nimbus DD2.2 + * and later versions. + */ + if ((PVR_VERS_MAJ(pvr) == 2) && + (PVR_VERS_MIN(pvr) >= 2)) + return true; + break; + case PROC_CHIP_P10: return true; + default: + return false; + } + } return false; } @@ -453,8 +477,8 @@ void imc_catalog_preload(void) if (proc_chip_quirks & QUIRK_MAMBO_CALLOUTS) return; - /* Enable only for power 9 */ - if (proc_gen != proc_gen_p9) + /* Enable only for power 9/10 */ + if (proc_gen < proc_gen_p9) return; compress_buf = malloc(MAX_COMPRESSED_IMC_DTB_SIZE); @@ -559,6 +583,17 @@ static int setup_imc_scoms(void) IMC_TRACE_CPMC2SEL_VAL, IMC_TRACE_BUFF_SIZE); return 0; + case proc_gen_p10: + CORE_IMC_EVENT_MASK_ADDR = CORE_IMC_EVENT_MASK_ADDR_P10; + TRACE_IMC_ADDR = TRACE_IMC_ADDR_P10; + pdbar_scom_index = pdbar_scom_index_p10; + htm_scom_index = htm_scom_index_p10; + trace_scom_val = TRACE_IMC_SCOM(IMC_TRACE_CPMC1, + IMC_TRACE_CPMCLOAD_VAL, + IMC_TRACE_CPMC1SEL_VAL, + IMC_TRACE_CPMC2SEL_VAL, + IMC_TRACE_BUFF_SIZE); + return 0; default: prerror("%s: Unknown cpu type\n", __func__); break; @@ -586,8 +621,8 @@ void imc_init(void) goto imc_mambo; } - /* Enable only for power 9 */ - if (proc_gen != proc_gen_p9) + /* Enable only for power 9/10 */ + if (proc_gen < proc_gen_p9) return; if (!imc_xz) @@ -720,6 +755,9 @@ static uint32_t get_imc_scom_addr_for_core(int core, uint64_t addr) case proc_gen_p9: scom_addr = XSCOM_ADDR_P9_EC(core, addr); return scom_addr; + case proc_gen_p10: + scom_addr = XSCOM_ADDR_P10_EC(core, addr); + return scom_addr; default: return 0; } @@ -734,6 +772,9 @@ static uint32_t get_imc_scom_addr_for_quad(int core, uint64_t addr) case proc_gen_p9: scom_addr = XSCOM_ADDR_P9_EQ(core, addr); return scom_addr; + case proc_gen_p10: + scom_addr = XSCOM_ADDR_P10_EQ(core, addr); + return scom_addr; default: return 0; } |