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author | Oliver O'Halloran <oohall@gmail.com> | 2019-08-07 16:24:35 +1000 |
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committer | Oliver O'Halloran <oohall@gmail.com> | 2019-08-16 15:51:55 +1000 |
commit | b03906a990fa3fe5f12e3eaf24a2fac370efb81e (patch) | |
tree | f353575f8984bbfb05d6f83786682e968b60b40f /hw/imc.c | |
parent | abf3e4c6a5349f7d25822f0a558f9b8cf71678cc (diff) | |
download | skiboot-b03906a990fa3fe5f12e3eaf24a2fac370efb81e.zip skiboot-b03906a990fa3fe5f12e3eaf24a2fac370efb81e.tar.gz skiboot-b03906a990fa3fe5f12e3eaf24a2fac370efb81e.tar.bz2 |
include/xscom: Use the name EQ rather than EP
The P9 pervasive spec uses the term "EP" to refer to the combination of
an EQ chiplet and its two child EX chiplets. Nothing else seems to use
the term EP and in Skiboot all the uses of the XSCOM_ADDR_P9_EP() macro
are to translate the address of EQ specific SCOM registers.
Change the name of our address calculation macros to match the general
terminology to make what it does clearer.
Cc: Anju T Sudhakar <anju@linux.vnet.ibm.com>
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
Diffstat (limited to 'hw/imc.c')
-rw-r--r-- | hw/imc.c | 12 |
1 files changed, 6 insertions, 6 deletions
@@ -699,7 +699,7 @@ static int64_t opal_imc_counters_init(uint32_t type, uint64_t addr, uint64_t cpu if (xscom_write(c->chip_id, - XSCOM_ADDR_P9_EP(phys_core_id, + XSCOM_ADDR_P9_EQ(phys_core_id, pdbar_scom_index[port_id]), (u64)(CORE_IMC_PDBAR_MASK & addr))) { prerror("error in xscom_write for pdbar\n"); @@ -710,7 +710,7 @@ static int64_t opal_imc_counters_init(uint32_t type, uint64_t addr, uint64_t cpu if (wakeup_engine_state == WAKEUP_ENGINE_PRESENT) { struct proc_chip *chip = get_chip(c->chip_id); - scoms = XSCOM_ADDR_P9_EP(phys_core_id, + scoms = XSCOM_ADDR_P9_EQ(phys_core_id, pdbar_scom_index[port_id]); ret = stop_api_init(chip, phys_core_id, scoms, (u64)(CORE_IMC_PDBAR_MASK & addr), @@ -743,7 +743,7 @@ static int64_t opal_imc_counters_init(uint32_t type, uint64_t addr, uint64_t cpu } if (xscom_write(c->chip_id, - XSCOM_ADDR_P9_EP(phys_core_id, + XSCOM_ADDR_P9_EQ(phys_core_id, htm_scom_index[port_id]), (u64)CORE_IMC_HTM_MODE_DISABLE)) { prerror("error in xscom_write for htm mode\n"); @@ -779,7 +779,7 @@ static int64_t opal_imc_counters_init(uint32_t type, uint64_t addr, uint64_t cpu } } if (xscom_write(c->chip_id, - XSCOM_ADDR_P9_EP(phys_core_id, htm_scom_index[port_id]), + XSCOM_ADDR_P9_EQ(phys_core_id, htm_scom_index[port_id]), (u64)CORE_IMC_HTM_MODE_DISABLE)) { prerror("IMC-trace: error in xscom_write for htm mode\n"); return OPAL_HARDWARE; @@ -845,7 +845,7 @@ static int64_t opal_imc_counters_start(uint32_t type, uint64_t cpu_pir) * to count with the previous initialization. */ if (xscom_write(c->chip_id, - XSCOM_ADDR_P9_EP(phys_core_id, + XSCOM_ADDR_P9_EQ(phys_core_id, htm_scom_index[port_id]), (u64)CORE_IMC_HTM_MODE_ENABLE)) { prerror("IMC OPAL_start: error in xscom_write for htm_mode\n"); @@ -905,7 +905,7 @@ static int64_t opal_imc_counters_stop(uint32_t type, uint64_t cpu_pir) * bits 4-9 of the HTM_MODE scom port. */ if (xscom_write(c->chip_id, - XSCOM_ADDR_P9_EP(phys_core_id, + XSCOM_ADDR_P9_EQ(phys_core_id, htm_scom_index[port_id]), (u64) CORE_IMC_HTM_MODE_DISABLE)) { prerror("error in xscom_write for htm_mode\n"); |