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authorAruna Balakrishnaiah <aruna@linux.vnet.ibm.com>2014-07-31 14:46:06 +0530
committerBenjamin Herrenschmidt <benh@kernel.crashing.org>2014-08-01 16:02:27 +1000
commite810dcbc09c375a39ce36f461eb0cc2f7e9a1aed (patch)
tree18590f39e6e997c4826a998a12c03c7f86239139 /hdata/spira.h
parent025184d5cb8626cd50ac28982d001f92f66a38e2 (diff)
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ATTN: Set up attention area to handle attention
At present CPU control area ntuple in SPIRA structure is NULL. ATTN component in Service Processor side checks for this field and if its empty, it logs hardcoded SRC (0xBB821410) and generates SYSDUMP. So we have 1 SRC for all failure (assert call) from OPAL side. This makes difficult to debug the issue. Service processor provides attention area interface (FIPS PHyp Attentions spec), so that we can pass SRC and user data (error message) to service processor. This will helps us identify different failures in OPAL. This patch enables attention area and provides interface (update_sp_attn_area()) to add src and user data (error message) through assert macro. Attention SRC format: 1st byte - Opal src type 2-4 bytes - Holds the address of the assert function call Signed-off-by: Aruna Balakrishnaiah <aruna@linux.vnet.ibm.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Diffstat (limited to 'hdata/spira.h')
-rw-r--r--hdata/spira.h32
1 files changed, 32 insertions, 0 deletions
diff --git a/hdata/spira.h b/hdata/spira.h
index 93239d0..fa73452 100644
--- a/hdata/spira.h
+++ b/hdata/spira.h
@@ -537,6 +537,38 @@ struct cechub_io_hub {
#define IOKID_KW_VPD 1
/*
+ * CPU Controls Legacy Structure
+ */
+struct cpu_ctl_legacy {
+ __be64 addr;
+ __be64 size;
+} __packed;
+
+/*
+ * CPU Control Legacy table
+ *
+ * Format of this table is defined in FIPS PHYP Attn spec.
+ */
+struct cpu_ctl_legacy_table {
+ struct cpu_ctl_legacy spat;
+ struct cpu_ctl_legacy sp_attn_area1;
+ struct cpu_ctl_legacy sp_attn_area2;
+ struct cpu_ctl_legacy hsr_area;
+ struct cpu_ctl_legacy reserved[12];
+} __packed;
+
+/*
+ * CPU Controls Header Structure
+ */
+#define CPU_CTL_HDIF_SIG "CPUCTL"
+struct cpu_ctl_init_data {
+ struct HDIF_common_hdr hdr;
+ struct HDIF_idata_ptr cpu_ctl;
+ uint8_t reserved[8];
+ struct cpu_ctl_legacy_table cpu_ctl_lt;
+} __packed __align(0x10);
+
+/*
* Slot Location Code Array (aka SLCA)
*
* This is a pile of location codes referenced by various other