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| author | Reza Arbab <arbab@linux.ibm.com> | 2019-09-03 14:49:22 -0500 |
|---|---|---|
| committer | Oliver O'Halloran <oohall@gmail.com> | 2019-09-06 16:57:53 +1000 |
| commit | 3f5ecfb385efda41e57a144d18a3a2fbca255d2c (patch) | |
| tree | 091671a58e04276abded65fd99f61e796b789f8f /external | |
| parent | cc02885770f63d00d2483be4e1627d2cadfffa8a (diff) | |
| download | skiboot-3f5ecfb385efda41e57a144d18a3a2fbca255d2c.zip skiboot-3f5ecfb385efda41e57a144d18a3a2fbca255d2c.tar.gz skiboot-3f5ecfb385efda41e57a144d18a3a2fbca255d2c.tar.bz2 | |
devicetree: Remove lpc interrupt properties
After commit 7b12d5489fcf ("hw/lpc: Configure SerIRQ interrupts on
P9P"), we abort on p9p Simics:
[ 1486.000029845,3] Duplicate property "interrupt-map" in node /lpcm-opb@6030000000000/lpc@f0000000
[ 1487.000158147,0] Aborting!
CPU 0000 Backtrace:
S: 0000000031c13940 R: 0000000030013d18 .backtrace+0x5c
S: 0000000031c139f0 R: 000000003001dbf8 ._abort+0x60
S: 0000000031c13a80 R: 000000003002d448 .new_property+0x94
S: 0000000031c13b20 R: 000000003002d5e8 .dt_add_property+0xd0
S: 0000000031c13bc0 R: 000000003004202c .lpc_create_int_map+0xa4
S: 0000000031c13da0 R: 0000000030043748 .lpc_finalize_interrupts+0x94
S: 0000000031c13e30 R: 0000000030015d18 .main_cpu_entry+0x620
S: 0000000031c13f00 R: 0000000030002740 boot_entry+0x1b8
Since skiboot creates these interrupt properties now, and always has on
older p9 systems, remove them from the input device tree.
Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
Diffstat (limited to 'external')
| -rw-r--r-- | external/devicetree/p9.dts | 16 |
1 files changed, 1 insertions, 15 deletions
diff --git a/external/devicetree/p9.dts b/external/devicetree/p9.dts index fac348b..fab7ffa 100644 --- a/external/devicetree/p9.dts +++ b/external/devicetree/p9.dts @@ -140,7 +140,7 @@ compatible = "ibm,power9-xive-x"; }; - PSI_X0: psihb@5012900 { + psihb@5012900 { reg = <0x5012900 0x100>; compatible = "ibm,power9-psihb-x", "ibm,psihb-x"; @@ -192,20 +192,6 @@ 0x0 0x0 0xe0000000 0x10000000 /* MEM space */ 0x1 0x0 0xd0010000 0x00010000 /* IO space */ >; - /* - * We currently only support level interrupts on the LPC, - * we use 1 cell. - */ - #interrupt-cells = <0x1>; - - /* - * Route the LPC interrupts to one of the 4 supported - * PSI interrupt inputs [7...10]. - */ - interrupt-map = <0x0 0x0 0x4 &PSI_X0 0x8 - 0x0 0x0 0xa &PSI_X0 0x9>; - interrupt-map-mask = <0x0 0x0 0xff>; - /* Devices on the LPC bus go here */ serial@i3f8 { |