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| author | Nicholas Piggin <npiggin@gmail.com> | 2017-09-20 16:56:03 +1000 |
|---|---|---|
| committer | Stewart Smith <stewart@linux.vnet.ibm.com> | 2017-09-20 23:25:01 -0500 |
| commit | 5e09fe1f19d3f56b1cebb44439da5b5de6e1fccd (patch) | |
| tree | 159d5c1c26a8068df3ec6cc623f5db7e3bfa8310 /doc | |
| parent | 5779c11fdc57c4dc474beb00f044f34ec1c58368 (diff) | |
| download | skiboot-5e09fe1f19d3f56b1cebb44439da5b5de6e1fccd.zip skiboot-5e09fe1f19d3f56b1cebb44439da5b5de6e1fccd.tar.gz skiboot-5e09fe1f19d3f56b1cebb44439da5b5de6e1fccd.tar.bz2 | |
core: POWER9 implement OPAL_SIGNAL_SYSTEM_RESET
This implements OPAL_SIGNAL_SYSTEM_RESET, using scom registers to
quiesce the target thread and raise a system reset exception on it.
It has been tested on DD2 with stop0 ESL=0 and ESL=1 shallow power
saving modes.
DD1 is not implemented because it is sufficiently different as to
make support difficult.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
[stewart@linux.vnet.ibm.com: fixup hdat_to_dt test]
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
Diffstat (limited to 'doc')
| -rw-r--r-- | doc/opal-api/opal-signal-system-reset-145.rst | 26 |
1 files changed, 16 insertions, 10 deletions
diff --git a/doc/opal-api/opal-signal-system-reset-145.rst b/doc/opal-api/opal-signal-system-reset-145.rst index 3ddb684..28e5e2f 100644 --- a/doc/opal-api/opal-signal-system-reset-145.rst +++ b/doc/opal-api/opal-signal-system-reset-145.rst @@ -9,12 +9,13 @@ OPAL_SIGNAL_SYSTEM_RESET This OPAL call causes the specified cpu(s) to be reset to the system reset exception handler (0x100). -The exact contents of system registers (e.g., SRR1 wakeup causes) may -vary depending on implementation and should not be relied upon. +The SRR1 register will indicate a power-saving wakeup when appropriate, +and the wake reason will be System Reset (see Power ISA). -Resetting active threads on the same core as this call is run may -not be supported by some platforms. In that case, OPAL_PARTIAL will be -returned and NONE of the interrupts will be delivered. +This interrupt may not be recoverable in some cases (e.g., if it is +raised when the target has MSR[RI]=0), so it should not be used in +normal operation, but only for crashing, debugging, and similar +exceptional cases. Arguments --------- @@ -28,18 +29,23 @@ Arguments Returns ------- OPAL_SUCCESS - The power down was updated successful. + The system reset requests to target CPU(s) was successful. This returns + asynchronously without acknowledgement from targets that system reset + interrupt processing has completed or even started. OPAL_PARAMETER A parameter was incorrect. OPAL_HARDWARE - Hardware indicated failure during reset. + Hardware indicated failure during reset, some or all of the target CPUs + may have the system reset delivered. + +OPAL_CONSTRAINED + Platform does not support broadcast operations. OPAL_PARTIAL - Platform can not reset all requested CPUs at this time. This requires - platform-specific code to work around, otherwise to be treated as - failure. No CPUs are reset. + Platform can not reset sibling threads on the same core as requested. + None of the specified CPUs are reset in this case. OPAL_UNSUPPORTED This processor/platform is not supported. |