add nx-842 coproc support

Add support for the 842 hw memory compression engine in the NX Coprocessor.
This moves the existing RNG support into its own nx-rng.c file, adds 842
support in a nx-842.c file, and creates a nx-crypto.c file to configure and
disable the crypto engines (which are not supported yet).

New nodes are created for each 842 engine found.  This does not actually
process any of the data or drive the 842 engines, it only configures
registers to set up and enable/disable the engines appropriately, and
creates new nodes so the OS can drive the 842 engines.

Signed-off-by: Dan Streetman <ddstreet@ieee.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>

1 files changed, 47 insertions, 0 deletions

diff --git a/doc/device-tree/nx.txt b/doc/device-tree/nx.txt
new file mode 100644
index 0000000..6c48956
--- /dev/null
+++ b/doc/device-tree/nx.txt
@@ -0,0 +1,47 @@
+Nest (NX) Accelerator Coprocessor
+---------------------------------
+
+The NX coprocessor is present in P7+ or later processors.  Each NX node
+represents a unique NX coprocessor.  The nodes are located under an
+xscom node, as:
+
+/xscom@<xscom_addr>/nx@<nx_addr>
+
+With unique xscom and nx addresses.  Their compatible node contains
+"ibm,power-nx".  There is nothing that the OS should directly do with the
+NX nodes, instead the specific coprocessor nodes should be used, as
+described below.
+
+
+NX RNG Coprocessor
+------------------
+
+This is the Random Number Generator (RNG) coprocessor, which is a part
+of each NX coprocessor.  Each node represents a unique RNG coprocessor.
+The nodes are located at:
+
+/hwrng@<addr>		: RNG at address <addr>
+ibm,chip-id		: chip id where the RNG is
+reg			: address of the register to read from
+
+Each read from the RNG register will provide a new random number.
+
+
+NX 842 Coprocessor
+------------------
+
+This is the memory compression coprocessor, which uses the IBM proprietary
+842 compression algorithm and format.  Each node represents a unique 842
+coprocessor.  The nodes are located at:
+
+/ibm,nx842-powernv#<chip-id>	: 842 coprocessor on chip <chip-id>
+ibm,chip-id			: chip id where the 842 is
+ibm,coprocessor-type		: CT value common to all 842 coprocessors
+ibm,coprocessor-instance	: CI value unique to all 842 coprocessors
+
+Access to the coprocessor requires using the ICSWX instruction, which uses
+a specific format including a Coprocessor Type (CT) and Coprocessor Instance (CI)
+value to address each request to the right coprocessor.  The system should
+use the CT and CI values for a particular node to communicate with it.  For
+all 842 coprocessors in the system, the CT value will (should) be the same,
+while each will have a different CI value.