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| author | Benjamin Herrenschmidt <benh@kernel.crashing.org> | 2016-08-09 16:38:14 +1000 |
|---|---|---|
| committer | Stewart Smith <stewart@linux.vnet.ibm.com> | 2016-08-11 19:54:22 +1000 |
| commit | d0a3ec6aea455d8b564f62679ff6f69f91ea7896 (patch) | |
| tree | e1420cf1654e1dfd60ebc5dd8712a6f6f740933d /doc/device-tree | |
| parent | c8fc681aa2ed5dc5584518d213eeecb2eef7b22c (diff) | |
| download | skiboot-d0a3ec6aea455d8b564f62679ff6f69f91ea7896.zip skiboot-d0a3ec6aea455d8b564f62679ff6f69f91ea7896.tar.gz skiboot-d0a3ec6aea455d8b564f62679ff6f69f91ea7896.tar.bz2 | |
psi: On p9, create an interrupt-map for routing PSI interrupts
This will provide the global IRQ numbers for all 16 PSI inputs (though
we don't really care about 0 here). We can then express them in the
device-tree as relative to the PSI bridge. Among others, that allows
us to express the external interrupt and the LPC interrupt using a
fixed numbering scheme.
The example device-tree is updated to route them all to the LPC0
input which corresponds to what the LPC code does at the moment.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
Diffstat (limited to 'doc/device-tree')
| -rw-r--r-- | doc/device-tree/examples/power9-phb4.dts | 28 |
1 files changed, 27 insertions, 1 deletions
diff --git a/doc/device-tree/examples/power9-phb4.dts b/doc/device-tree/examples/power9-phb4.dts index 8da1cbc..a845a86 100644 --- a/doc/device-tree/examples/power9-phb4.dts +++ b/doc/device-tree/examples/power9-phb4.dts @@ -153,9 +153,18 @@ compatible = "ibm,power9-xive-x"; }; - psihb@5012900 { + PSI_X0 : psihb@5012900 { reg = <0x5012900 0x100>; compatible = "ibm,power9-psihb-x", "ibm,psihb-x"; + + /* This acts as an interrupt remapper for the 16 + * interrupts coming into the PSI HB. + * OPAL will generate the corresponding interrupt-map + * property with the final XIVE numbers + */ + #interrupt-cells = <1>; + #address-cells = <0>; + #interrupt-map-mask = < 0xff >; }; }; @@ -185,6 +194,23 @@ ranges = < 3 0 0xf0000000 0x10000000 /* FW space */ 0 0 0xe0000000 0x10000000 /* MEM space */ 1 0 0xd0010000 0x00010000 /* IO space */ >; + + /* We currently only support level interrupts on the LPC, + * we use 1 cell. + */ + #interrupt-cells = <1>; + + /* Route the LPC interrupts to one of the 4 supported + * PSI interrupt inputs [7...10]. + */ + interrupt-map = < 0 0 4 &PSI_X0 7 + 0 0 10 &PSI_X0 7>; + interrupt-map-mask = < 0 0 0xff >; + + /* + * Devices on the LPC bus go here + */ + serial@i3f8 { compatible = "ns16550"; reg = < 1 0x3f8 0x10 >; |