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authorMichael Neuling <mikey@neuling.org>2017-05-02 13:23:06 +1000
committerStewart Smith <stewart@linux.vnet.ibm.com>2017-05-10 16:58:18 +1000
commit5f67c1e253788691d376e4e639d4a6e7785efa55 (patch)
treeafebf05ed7e6bb84120c8bd5d7306c39545066bd /core
parent4fbdcf6bd10b1c93977e789a42bb54b98458acd6 (diff)
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Add global physical memory map
This adds a global map for allocating physical memory address. This centralises physical memory space allocations into one location rather than spread through, PHB, XIVE, NX etc. This adds a new call phys_map_get() which takes a chip, type and index and returns a address and size for the region to be used. An error in a call to this function crashes skiboot. This is done since bogus calls here are going to be hit by developers not users and they need to be fixed. Currently only P9 is implemented but other chips should be easy to add. On P9 BARs are generally set by skiboot. On P8 this was done by hostboot so this is not needed there. This just adds the infrastructure. User (PHB4, XIVE etc) will be migrated in subsequent patches. Suggested-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
Diffstat (limited to 'core')
-rw-r--r--core/init.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/core/init.c b/core/init.c
index 9d4d185..dce10fd 100644
--- a/core/init.c
+++ b/core/init.c
@@ -47,6 +47,7 @@
#include <nvram.h>
#include <libstb/stb.h>
#include <libstb/container.h>
+#include <phys-map.h>
enum proc_gen proc_gen;
unsigned int pcie_max_link_speed;
@@ -828,6 +829,9 @@ void __noreturn __nomcount main_cpu_entry(const void *fdt)
*/
opal_table_init();
+ /* Init the physical map table so we can start mapping things */
+ phys_map_init();
+
/*
* If we are coming in with a flat device-tree, we expand it
* now. Else look for HDAT and create a device-tree from them