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| author | Michael Neuling <mikey@neuling.org> | 2016-05-02 15:26:21 +1000 |
|---|---|---|
| committer | Stewart Smith <stewart@linux.vnet.ibm.com> | 2016-05-10 16:04:51 +1000 |
| commit | 591feeef8353c8a0ee73e42ff1538cf436c5fd1d (patch) | |
| tree | 224bfb9fbed30b06eede81bd82d0506d91f24bb3 /core | |
| parent | 3ff350343a67cd1897f37684613468a5f849ac1b (diff) | |
| download | skiboot-591feeef8353c8a0ee73e42ff1538cf436c5fd1d.zip skiboot-591feeef8353c8a0ee73e42ff1538cf436c5fd1d.tar.gz skiboot-591feeef8353c8a0ee73e42ff1538cf436c5fd1d.tar.bz2 | |
Add base POWER9 support
Add PVR detection, chip id and other misc bits for POWER9.
POWER9 changes the location of the HILE and attn enable bits in the
HID0 register, so add these definitions also.
Signed-off-by: Michael Neuling <mikey@neuling.org>
[stewart@linux.vnet.ibm.com: Fix Numbus typo, hdata_to_dt build fixes]
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
Diffstat (limited to 'core')
| -rw-r--r-- | core/affinity.c | 2 | ||||
| -rw-r--r-- | core/chip.c | 12 | ||||
| -rw-r--r-- | core/cpu.c | 12 |
3 files changed, 23 insertions, 3 deletions
diff --git a/core/affinity.c b/core/affinity.c index df708a8..9f489d3 100644 --- a/core/affinity.c +++ b/core/affinity.c @@ -120,6 +120,8 @@ void add_core_associativity(struct cpu_thread *cpu) core_id = (cpu->pir >> 2) & 0x7; else if (proc_gen == proc_gen_p8) core_id = (cpu->pir >> 3) & 0xf; + else if (proc_gen == proc_gen_p9) + core_id = (cpu->pir >> 2) & 0x1f; else return; diff --git a/core/chip.c b/core/chip.c index 49d2f1f..4d01b92 100644 --- a/core/chip.c +++ b/core/chip.c @@ -24,7 +24,9 @@ enum proc_chip_quirks proc_chip_quirks; uint32_t pir_to_chip_id(uint32_t pir) { - if (proc_gen == proc_gen_p8) + if (proc_gen == proc_gen_p9) + return P9_PIR2GCID(pir); + else if (proc_gen == proc_gen_p8) return P8_PIR2GCID(pir); else return P7_PIR2GCID(pir); @@ -32,7 +34,9 @@ uint32_t pir_to_chip_id(uint32_t pir) uint32_t pir_to_core_id(uint32_t pir) { - if (proc_gen == proc_gen_p8) + if (proc_gen == proc_gen_p9) + return P9_PIR2COREID(pir); + else if (proc_gen == proc_gen_p8) return P8_PIR2COREID(pir); else return P7_PIR2COREID(pir); @@ -40,7 +44,9 @@ uint32_t pir_to_core_id(uint32_t pir) uint32_t pir_to_thread_id(uint32_t pir) { - if (proc_gen == proc_gen_p8) + if (proc_gen == proc_gen_p9) + return P9_PIR2THREADID(pir); + else if (proc_gen == proc_gen_p8) return P8_PIR2THREADID(pir); else return P7_PIR2THREADID(pir); @@ -465,6 +465,12 @@ void init_boot_cpu(void) hid0_hile = SPR_HID0_POWER8_HILE; hid0_attn = SPR_HID0_POWER8_ENABLE_ATTN; break; + case PVR_TYPE_P9: + proc_gen = proc_gen_p9; + hile_supported = true; + hid0_hile = SPR_HID0_POWER9_HILE; + hid0_attn = SPR_HID0_POWER9_ENABLE_ATTN; + break; default: proc_gen = proc_gen_unknown; } @@ -483,6 +489,12 @@ void init_boot_cpu(void) prlog(PR_INFO, "CPU: P8 generation processor" "(max %d threads/core)\n", cpu_thread_count); break; + case proc_gen_p9: + cpu_thread_count = 4; + cpu_max_pir = SPR_PIR_P9_MASK; + prlog(PR_INFO, "CPU: P9 generation processor" + "(max %d threads/core)\n", cpu_thread_count); + break; default: prerror("CPU: Unknown PVR, assuming 1 thread\n"); cpu_thread_count = 1; |