diff options
author | Nicholas Piggin <npiggin@gmail.com> | 2019-01-08 00:04:21 +1000 |
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committer | Stewart Smith <stewart@linux.ibm.com> | 2019-02-13 14:36:43 +1100 |
commit | d25287a167fda2f66efc27b56d6ecd77c2239a45 (patch) | |
tree | 31a8cd5182cc924b279335200ca092210486c1b6 /core | |
parent | 02aea4c8760ae9a9913189b9cb93bb8c109e46ed (diff) | |
download | skiboot-d25287a167fda2f66efc27b56d6ecd77c2239a45.zip skiboot-d25287a167fda2f66efc27b56d6ecd77c2239a45.tar.gz skiboot-d25287a167fda2f66efc27b56d6ecd77c2239a45.tar.bz2 |
core/fast-reboot: improve NMI handling during fast reset
Improve sreset and MCE handling in fast reboot. Switch the HILE bit
off before copying OPAL's exception vectors, so NMIs can be handled
properly. Also disable MSR[ME] while the vectors are being overwritten.
Some of the remaining problem cases are documented in comments.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
Diffstat (limited to 'core')
-rw-r--r-- | core/fast-reboot.c | 34 |
1 files changed, 34 insertions, 0 deletions
diff --git a/core/fast-reboot.c b/core/fast-reboot.c index 02ef846..eb1b348 100644 --- a/core/fast-reboot.c +++ b/core/fast-reboot.c @@ -170,8 +170,42 @@ void fast_reboot(void) cpu->save_r1 = 0; } + /* + * Move SPRs and exception vectors back to OPAL-mode while all + * others are quiesced. MSR[ME] is disabled while these are switched, + * but system reset can not be blocked -- in theory an sreset coming + * from the BMC or SPE could crash here. + */ + disable_machine_check(); + + /* + * Primarily we want to fix up the HID bits here to allow the OPAL + * exception handlers to work. Machine check would be the important + * one. + * + * This is one case where a thread other than thread0 of the core + * may update the shared SPRs. All other threads are stopped, so + * there should be no races. + */ + init_shared_sprs(); + init_replicated_sprs(); + /* Restore skiboot vectors */ copy_exception_vectors(); + + /* + * Secondaries may still have an issue with machine checks if they have + * HILE set because the machine check exception does not FIXUP_ENDIAN. + * Adding that would trash CFAR however. So we have a window where + * if a secondary takes an interrupt before the HILE is fixed, it will + * crash. + */ + enable_machine_check(); + + /* + * sreset vector has a FIXUP_ENDIAN sequence at the start, so + * secondaries can cope. + */ copy_sreset_vector(); /* Send everyone else to 0x100 */ |