Remove POWER9N DD1 support

This is not a shipping product and is no longer supported by Linux
or other firmware components.

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Stewart Smith <stewart@linux.ibm.com>

3 files changed, 6 insertions, 21 deletions

diff --git a/core/cpu.c b/core/cpu.c
index a83f8ba..36655fe 100644
--- a/core/cpu.c
+++ b/core/cpu.c
@@ -610,11 +610,6 @@ void cpu_set_sreset_enable(bool enabled)
 		}
 
 	} else if (proc_gen == proc_gen_p9) {
-		/* Don't use sreset idle on DD1 (has a number of bugs) */
-		uint32_t version = mfspr(SPR_PVR);
-		if (is_power9n(version) && (PVR_VERS_MAJ(version) == 1))
-			return;
-
 		sreset_enabled = enabled;
 		sync();
 		/*
@@ -643,11 +638,6 @@ void cpu_set_ipi_enable(bool enabled)
 		}
 
 	} else if (proc_gen == proc_gen_p9) {
-		/* Don't use doorbell on DD1 (requires darn for msgsync) */
-		uint32_t version = mfspr(SPR_PVR);
-		if (is_power9n(version) && (PVR_VERS_MAJ(version) == 1))
-			return;
-
 		ipi_enabled = enabled;
 		sync();
 		if (!enabled)
@@ -1014,6 +1004,11 @@ void init_boot_cpu(void)
 		cpu_max_pir = mfspr(SPR_PIR);
 	}
 
+	if (is_power9n(pvr) && (PVR_VERS_MAJ(pvr) == 1)) {
+		prerror("CPU: POWER9N DD1 is not supported\n");
+		abort();
+	}
+
 	prlog(PR_DEBUG, "CPU: Boot CPU PIR is 0x%04x PVR is 0x%08x\n",
 	      pir, pvr);
 
diff --git a/core/cpufeatures.c b/core/cpufeatures.c
index e9d2daf..1daa017 100644
--- a/core/cpufeatures.c
+++ b/core/cpufeatures.c
@@ -900,10 +900,7 @@ void dt_add_cpufeatures(struct dt_node *root)
 			cpu_name = "POWER9";
 
 		cpu_feature_isa = ISA_V3_0B;
-		if (is_power9n(version) && (PVR_VERS_MAJ(version) == 1)) {
-			/* P9N DD1 */
-			cpu_feature_cpu = CPU_P9_DD1;
-		} else if (is_power9n(version) &&
+		if (is_power9n(version) &&
 			   (PVR_VERS_MAJ(version) == 2)) {
 			/* P9N DD2.x */
 			cpu_feature_cpu = CPU_P9_DD2;
diff --git a/core/direct-controls.c b/core/direct-controls.c
index 04b93a1..1d0f681 100644
--- a/core/direct-controls.c
+++ b/core/direct-controls.c
@@ -851,18 +851,11 @@ int64_t opal_signal_system_reset(int cpu_nr)
 
 void direct_controls_init(void)
 {
-	uint32_t version;
-
 	if (chip_quirk(QUIRK_MAMBO_CALLOUTS))
 		return;
 
 	if (proc_gen != proc_gen_p9)
 		return;
 
-	/* DD1 has some sreset quirks we do not support */
-	version = mfspr(SPR_PVR);
-	if (is_power9n(version) && PVR_VERS_MAJ(version) == 1)
-		return;
-
 	opal_register(OPAL_SIGNAL_SYSTEM_RESET, opal_signal_system_reset, 1);
 }