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| author | Benjamin Herrenschmidt <benh@kernel.crashing.org> | 2018-05-11 19:06:58 +1000 |
|---|---|---|
| committer | Stewart Smith <stewart@linux.ibm.com> | 2018-05-24 04:03:19 -0500 |
| commit | 15d9f319978211045651a8c960db6a46ab52b1f4 (patch) | |
| tree | 7ee91d4895ac13c5c07cf20431a4b7dae592881d /core | |
| parent | 08992151641a24db5ff52ce3a4bd18714d5be700 (diff) | |
| download | skiboot-15d9f319978211045651a8c960db6a46ab52b1f4.zip skiboot-15d9f319978211045651a8c960db6a46ab52b1f4.tar.gz skiboot-15d9f319978211045651a8c960db6a46ab52b1f4.tar.bz2 | |
cpu: Use STOP1 on POWER9 for idle/sleep inside OPAL
The current code requests STOP3, which means it gets STOP2 in practice.
STOP2 has proven to occasionally be unreliable depending on FW
version and chip revision, it also requires a functional CME,
so instead, let's use STOP1. The difference is rather minimum
for something that is only used a few seconds during boot.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
Diffstat (limited to 'core')
| -rw-r--r-- | core/cpu.c | 8 |
1 files changed, 4 insertions, 4 deletions
@@ -409,14 +409,14 @@ static void cpu_idle_p9(enum cpu_wake_cause wake_on) if (sreset_enabled) { /* stop with EC=1 (sreset) and ESL=1 (enable thread switch). */ - /* PSSCR SD=0 ESL=1 EC=1 PSSL=0 TR=3 MTL=0 RL=3 */ + /* PSSCR SD=0 ESL=1 EC=1 PSSL=0 TR=3 MTL=0 RL=1 */ psscr = PPC_BIT(42) | PPC_BIT(43) | - PPC_BITMASK(54, 55) | PPC_BITMASK(62,63); + PPC_BITMASK(54, 55) | PPC_BIT(63); enter_p9_pm_state(psscr); } else { /* stop with EC=0 (resumes) which does not require sreset. */ - /* PSSCR SD=0 ESL=0 EC=0 PSSL=0 TR=3 MTL=0 RL=3 */ - psscr = PPC_BITMASK(54, 55) | PPC_BITMASK(62,63); + /* PSSCR SD=0 ESL=0 EC=0 PSSL=0 TR=3 MTL=0 RL=1 */ + psscr = PPC_BITMASK(54, 55) | PPC_BIT(63); enter_p9_pm_lite_state(psscr); } |