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| author | Benjamin Herrenschmidt <benh@kernel.crashing.org> | 2017-06-06 08:59:23 +1000 |
|---|---|---|
| committer | Stewart Smith <stewart@linux.vnet.ibm.com> | 2017-06-06 20:49:05 +1000 |
| commit | 9eb2ab74905ff59dd0de5fb3ece6b910863e8a31 (patch) | |
| tree | e9c33dae3bb3bcdda24a5fd0eeef6d67e859bddc /core/pci.c | |
| parent | 68d9e87c11b589d709bb86786703ccb5c68bd8f8 (diff) | |
| download | skiboot-9eb2ab74905ff59dd0de5fb3ece6b910863e8a31.zip skiboot-9eb2ab74905ff59dd0de5fb3ece6b910863e8a31.tar.gz skiboot-9eb2ab74905ff59dd0de5fb3ece6b910863e8a31.tar.bz2 | |
phb4: Block D-state power management on direct slots
As current revisions of PHB4 don't properly handle the resulting
L1 link transition.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
Diffstat (limited to 'core/pci.c')
| -rw-r--r-- | core/pci.c | 10 |
1 files changed, 10 insertions, 0 deletions
@@ -202,11 +202,21 @@ static void pci_init_aer_cap(struct phb *phb, struct pci_device *pd) pci_set_cap(pd, PCIECAP_ID_AER, pos, NULL, true); } +static void pci_init_pm_cap(struct phb *phb, struct pci_device *pd) +{ + int64_t pos; + + pos = pci_find_cap(phb, pd->bdfn, PCI_CFG_CAP_ID_PM); + if (pos > 0) + pci_set_cap(pd, PCI_CFG_CAP_ID_PM, pos, NULL, false); +} + void pci_init_capabilities(struct phb *phb, struct pci_device *pd) { pci_init_pcie_cap(phb, pd); pci_init_aer_cap(phb, pd); pci_init_iov_cap(phb, pd); + pci_init_pm_cap(phb, pd); } static struct pci_device *pci_scan_one(struct phb *phb, struct pci_device *parent, |