diff options
author | Vasant Hegde <hegdevasant@linux.vnet.ibm.com> | 2018-04-23 12:15:32 +0530 |
---|---|---|
committer | Stewart Smith <stewart@linux.ibm.com> | 2018-04-30 19:04:42 -0500 |
commit | d7e7bdcd4accff9fb75579b43be72bc3c201d161 (patch) | |
tree | 0641e6c0ec772449322c053024a70da759d51a24 /core/interrupts.c | |
parent | 6421fc56dc289c8d14a1ce9eddbb88d3687fbb77 (diff) | |
download | skiboot-d7e7bdcd4accff9fb75579b43be72bc3c201d161.zip skiboot-d7e7bdcd4accff9fb75579b43be72bc3c201d161.tar.gz skiboot-d7e7bdcd4accff9fb75579b43be72bc3c201d161.tar.bz2 |
SBE: Add timer support
SBE on P9 provides one shot programmable timer facility. We can use this
to implement OPAL timers and hence limit the reliance on the Linux
heartbeat (similar to HW timer facility provided by SLW on P8).
Design:
- We will continue to run Linux heartbeat.
- Each chip has SBE. This patch always schedules timer on SBE on master chip.
- Start timer option starts new timer or modifies an active timer for the
specified timeout.
- SBE expects timeout value in microseconds. We track timeout value in TB.
Hence we convert tb to microseconds before sending request to SBE.
- We are requesting ack from SBE for timer message. It gaurantees that
SBE has scheduled timer.
- Disabling SBE timer
We expect SBE to send timer expiry interrupt whenever timer expires. We
wait for 10 more ms before disabling timer.
In future we can consider below alternative approaches:
- Presently SBE timer disable is permanent (until we reboot system).
SBE sends "I'm back" interrupt after reset. We can consider restarting
timer after SBE reset.
- Reset SBE and start timer again.
- Each chip has SBE. On multi chip system we can try to schedule timer
on different chip.
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
CC: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
Diffstat (limited to 'core/interrupts.c')
-rw-r--r-- | core/interrupts.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/core/interrupts.c b/core/interrupts.c index 4452511..5d7a68c 100644 --- a/core/interrupts.c +++ b/core/interrupts.c @@ -26,6 +26,7 @@ #include <ccan/str/str.h> #include <timer.h> #include <sbe-p8.h> +#include <sbe-p9.h> /* ICP registers */ #define ICP_XIRR 0x4 /* 32-bit access */ @@ -489,7 +490,7 @@ static int64_t opal_handle_interrupt(uint32_t isn, __be64 *outstanding_event_mas is->ops->interrupt(is, isn); /* Check timers if SBE timer isn't working */ - if (!p8_sbe_timer_ok()) + if (!p8_sbe_timer_ok() && !p9_sbe_timer_ok()) check_timers(true); /* Update output events */ |