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author | Oliver O'Halloran <oohall@gmail.com> | 2017-12-05 14:19:19 +1100 |
---|---|---|
committer | Stewart Smith <stewart@linux.vnet.ibm.com> | 2017-12-11 19:30:46 -0600 |
commit | 5bb9d6f1e7dc0e38beb1db8f9f032a926310beac (patch) | |
tree | 09cdae2bd55bf99e284d1b26c7e27d42023f7ac4 /core/init.c | |
parent | 22df7a1c73c933195c2a06418ebb3434c6e6b506 (diff) | |
download | skiboot-5bb9d6f1e7dc0e38beb1db8f9f032a926310beac.zip skiboot-5bb9d6f1e7dc0e38beb1db8f9f032a926310beac.tar.gz skiboot-5bb9d6f1e7dc0e38beb1db8f9f032a926310beac.tar.bz2 |
chiptod: Keep boot timestamps contiguous
Currently we reset the timebase value to (almost) zero when
synchronising the timebase of each chip to the Chip TOD network which
results in this:
[ 42.374813167,5] CPU: All 80 processors called in...
[ 2.222791151,5] FLASH: Found system flash: Macronix MXxxL51235F id:0
[ 2.222977933,5] BT: Interface initialized, IO 0x00e4
This patch modifies the chiptod_init() process to use the current
timebase value rather than resetting it to zero. This results in the
timestamps remaining contigious from the start of hostboot until
the petikernel starts. e.g.
[ 70.188811484,5] CPU: All 144 processors called in...
[ 72.458004252,5] FLASH: Found system flash: id:0
[ 72.458147358,5] BT: Interface initialized, IO 0x00e4
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
Reviewed-by: Vaidyanathan Srinivasan <svaidy@linux.vnet.ibm.com>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
Diffstat (limited to 'core/init.c')
-rw-r--r-- | core/init.c | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/core/init.c b/core/init.c index 2eeba75..9eb8e25 100644 --- a/core/init.c +++ b/core/init.c @@ -972,9 +972,11 @@ void __noreturn __nomcount main_cpu_entry(const void *fdt) cpu_set_sreset_enable(true); /* - * Synchronize time bases. Thi resets all the TB values to a small - * value (so they appear to go backward at this point), and synchronize - * all core timebases to the global ChipTOD network + * Synchronize time bases. Prior to chiptod_init() the timebase + * is free-running at a frequency based on the core clock rather + * than being synchronised to the ChipTOD network. This means + * that the timestamps in early boot might be a little off compared + * to wall clock time. */ chiptod_init(); |