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author | Benjamin Herrenschmidt <benh@kernel.crashing.org> | 2017-03-09 11:45:38 +1100 |
---|---|---|
committer | Stewart Smith <stewart@linux.vnet.ibm.com> | 2017-03-09 13:36:35 +1100 |
commit | 403b82555425a71121f7a62e58d37f57325f78d1 (patch) | |
tree | 1a818df7a02f142bdf55051aa39424b1f0590043 /asm | |
parent | 47a90f165b105434e5a3ef15b00ad3a7867a991b (diff) | |
download | skiboot-403b82555425a71121f7a62e58d37f57325f78d1.zip skiboot-403b82555425a71121f7a62e58d37f57325f78d1.tar.gz skiboot-403b82555425a71121f7a62e58d37f57325f78d1.tar.bz2 |
asm: Fix setting of LPCR:DPFD
We have code to set DPFD to 4 in init_shared_sprs, from the original
commit, based on recommendations from HW.
However, we immediately override this in init_replicated_sprs with
the value 7.
So let's remove the former and update the latter to set the value
to 4.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
Diffstat (limited to 'asm')
-rw-r--r-- | asm/head.S | 10 |
1 files changed, 2 insertions, 8 deletions
@@ -689,13 +689,7 @@ init_shared_sprs: /* TSCR: Recommended value by HW folks */ LOAD_IMM32(%r3,0x8ACC6880) mtspr SPR_TSCR, %r3 - mfspr %r3,SPR_LPCR - rldicr %r3,%r3,12,60 - ori %r3,%r3,4 - rldicr %r3,%r3,52,63 - mtspr SPR_LPCR,%r3 - sync - isync + /* HID0: Clear bit 13 (enable core recovery) * Clear bit 19 (HILE) */ @@ -729,7 +723,7 @@ init_shared_sprs: .global init_replicated_sprs init_replicated_sprs: /* LPCR: sane value */ - LOAD_IMM64(%r3,0x0070000000000004) + LOAD_IMM64(%r3,0x0040000000000004) mtspr SPR_LPCR, %r3 /* XXX TODO: Add more */ |