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| author | Nicholas Piggin <npiggin@gmail.com> | 2019-11-11 15:44:48 +1000 |
|---|---|---|
| committer | Oliver O'Halloran <oohall@gmail.com> | 2019-11-11 18:35:00 +1100 |
| commit | 3fbfb0e351cdeb9279aa2857046ecf0823b787dc (patch) | |
| tree | eb1564eaf99f4dbb1d21c6be55e813d3eafa0d83 /asm | |
| parent | bb445088d0dd11c2a1b749792e49ccdb1d6f6c33 (diff) | |
| download | skiboot-3fbfb0e351cdeb9279aa2857046ecf0823b787dc.zip skiboot-3fbfb0e351cdeb9279aa2857046ecf0823b787dc.tar.gz skiboot-3fbfb0e351cdeb9279aa2857046ecf0823b787dc.tar.bz2 | |
Remove dead POWER7 code
There are a number of proc_gen branches removed that are trivially
dead code and comments that refer to P7. As well as those:
- Oliver points out that add_xics_icps() must be unused on POWER8
because it asserts if number of threads > 4, so remove it.
- Change 16b7ae641 ("Remove POWER7 and POWER7+ support") removed all
references to opal_boot_trampoline, so remove that.
- It also removed the only non-trival choose_bus implementation, so
that is removed and its caller simplified.
- Remove the paca code, later CPUs use pcia.
Cc: Stewart Smith <stewart@flamingspork.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
Diffstat (limited to 'asm')
| -rw-r--r-- | asm/head.S | 10 |
1 files changed, 0 insertions, 10 deletions
@@ -861,16 +861,6 @@ hv_lid_load_table: .long 0 - /* The FSP seems to ignore our primary/secondary entry - * points and instead copy that bit down to 0x180 and - * patch the first instruction to get our expected - * boot CPU number. We ignore that patching for now and - * got to the same entry we use for pHyp and FDT HB. - */ -opal_boot_trampoline: - li %r27,-1 - ba boot_entry - __head - /* * * OPAL entry point from operating system |