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| author | Ryan Grimm <grimm@linux.ibm.com> | 2020-02-05 15:48:13 -0500 |
|---|---|---|
| committer | Oliver O'Halloran <oohall@gmail.com> | 2020-06-04 09:42:16 +1000 |
| commit | 37a369bbcb5a3f37de3affb77fc774375b83783e (patch) | |
| tree | 110748999cb04bc27cb60f79aee88816af8db0e3 /asm | |
| parent | 244a8daca45b3dc22d08e1dd17d201ebdbf62d58 (diff) | |
| download | skiboot-37a369bbcb5a3f37de3affb77fc774375b83783e.zip skiboot-37a369bbcb5a3f37de3affb77fc774375b83783e.tar.gz skiboot-37a369bbcb5a3f37de3affb77fc774375b83783e.tar.bz2 | |
Disable protected execution facility
This patch disables Protected Execution Faciltiy (PEF).
This software procedure is needed for the lab because Cronus will be
configured to bring the machine up with PEF on. Hostboot has a similar
procedure for running with PEF off.
Skiboot can run with PEF on but the kernel cannot; the kernel will take
a machine check when trying to write a protected resource, such as the
PTCR.
So, use this until we have an ultravisor, or if we want to use BML with
Cronus without UV = 1.
Signed-off-by: Ryan Grimm <grimm@linux.ibm.com>
Tested-by: Alistair Popple <alistair@popple.id.au>
[oliver: replaced bare urfid with a macro for toolchain compatibility]
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
Diffstat (limited to 'asm')
| -rw-r--r-- | asm/misc.S | 41 |
1 files changed, 41 insertions, 0 deletions
@@ -154,6 +154,7 @@ cleanup_global_tlb: #define PPC_INST_RVWINKLE .long 0x4c0003e4 #define PPC_INST_STOP .long 0x4c0002e4 +#define PPC_INST_URFID .long 0x4c000264 #define SAVE_GPR(reg,sp) std %r##reg,STACK_GPR##reg(sp) #define REST_GPR(reg,sp) ld %r##reg,STACK_GPR##reg(sp) @@ -255,3 +256,43 @@ enter_p9_pm_state: mtspr SPR_PSSCR,%r3 PPC_INST_STOP b . + +/* + * Exit UV mode and disable Protected Execution Facility. + * + * For each core, this should be run on all secondary threads first to bring + * them out of UV mode. Then, it is called by the primary thread to disable + * PEF and bring it out of UV mode. All threads will then be running in HV + * mode and the only way to re-enable UV mode is with a reboot. + * + * r3 = 1 if primary thread + * 0 if secondary thread + */ +.global exit_uv_mode +exit_uv_mode: + mfmsr %r4 + LOAD_IMM64(%r5, ~MSR_S) + and %r4,%r4,%r5 + mtspr SPR_USRR1,%r4 + + mfspr %r4,SPR_HSRR1 + and %r4,%r4,%r5 + mtspr SPR_HSRR1,%r3 + + mfspr %r4,SPR_SRR1 + and %r4,%r4,%r5 + mtspr SPR_SRR1,%r4 + + cmpdi %r3,1 + bne 1f + mfspr %r4, SPR_SMFCTRL + LOAD_IMM64(%r5, ~PPC_BIT(0)) + and %r4,%r4,%r5 + mtspr SPR_SMFCTRL,%r4 +1: + isync + + mflr %r4 + mtspr SPR_USRR0,%r4 + + PPC_INST_URFID |