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author | Nicholas Piggin <npiggin@gmail.com> | 2019-01-08 00:04:27 +1000 |
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committer | Stewart Smith <stewart@linux.ibm.com> | 2019-02-13 14:36:44 +1100 |
commit | 22524e9017445a08d63733ae5a8c75d9126bdb28 (patch) | |
tree | 108e57e4df4762e0773a9c2615fcc70fac7e0408 /asm/head.S | |
parent | 8a43bf86b7d4346521bd4ebc15eb3809d3d27adb (diff) | |
download | skiboot-22524e9017445a08d63733ae5a8c75d9126bdb28.zip skiboot-22524e9017445a08d63733ae5a8c75d9126bdb28.tar.gz skiboot-22524e9017445a08d63733ae5a8c75d9126bdb28.tar.bz2 |
core/exceptions: allow recoverable sreset exceptions
This requires implementing the MSR[RI] bit. Then just allow all
non-fatal sreset exceptions to recover.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
Diffstat (limited to 'asm/head.S')
-rw-r--r-- | asm/head.S | 4 |
1 files changed, 4 insertions, 0 deletions
@@ -175,7 +175,9 @@ _exception: stw %r3,STACK_DSISR(%r1) std %r4,STACK_DAR(%r1) mfmsr %r3 + li %r4,MSR_RI std %r3,STACK_MSR(%r1) + mtmsrd %r4,1 mfspr %r3,SPR_HSRR0 mfspr %r4,SPR_HSRR1 std %r3,STACK_HSRR0(%r1) @@ -276,6 +278,8 @@ exception_entry_foo: REST_GPR(29,%r1) REST_GPR(30,%r1) REST_GPR(31,%r1) + li %r3,0 + mtmsrd %r3,1 /* Clear MSR[RI] */ ld %r3,STACK_SRR0(%r1) mtspr SPR_SRR0,%r3 ld %r3,STACK_SRR1(%r1) |