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author | Nicholas Piggin <npiggin@gmail.com> | 2019-04-12 14:05:29 +1000 |
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committer | Stewart Smith <stewart@linux.ibm.com> | 2019-04-17 15:56:34 +1000 |
commit | 53ef0db6e2efbf9678699db4a57df26cdd89e462 (patch) | |
tree | 926c52210c2b53aeb73e910b7c0cb145e7d15ab0 /asm/head.S | |
parent | ac226d2c98ad95db44e1f2c27775c1b557af876b (diff) | |
download | skiboot-53ef0db6e2efbf9678699db4a57df26cdd89e462.zip skiboot-53ef0db6e2efbf9678699db4a57df26cdd89e462.tar.gz skiboot-53ef0db6e2efbf9678699db4a57df26cdd89e462.tar.bz2 |
asm/head.S: set POWER9 radix HID bit at entry
When running in virtual memory mode, the radix MMU hid bit should not
be changed, so set this in the initial boot SPR setup.
As a side effect, fast reboot also has HID0:RADIX bit set by the
shared spr init, so no need for an explicit call.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
Diffstat (limited to 'asm/head.S')
-rw-r--r-- | asm/head.S | 3 |
1 files changed, 3 insertions, 0 deletions
@@ -766,9 +766,12 @@ init_shared_sprs: mtspr SPR_TSCR, %r3 /* HID0: Clear bit 5 (enable core recovery) * Clear bit 4 (HILE) + * Set bit 8 (radix) */ mfspr %r3,SPR_HID0 li %r0,1 + sldi %r4,%r0,(63-8) + or %r3,%r3,%r4 sldi %r4,%r0,(63-5) sldi %r5,%r0,(63-4) or %r0,%r4,%r5 |