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| author | Cédric Le Goater <clg@kaod.org> | 2021-08-04 12:51:22 +0530 |
|---|---|---|
| committer | Vasant Hegde <hegdevasant@linux.vnet.ibm.com> | 2021-08-06 12:29:01 +0530 |
| commit | e59cbfa720845c09b7b601e03dd75b73ab4baf8d (patch) | |
| tree | 0757c127a688011cabe7404c7f260e078c479efb | |
| parent | 4bd7d84afe46c845f3e1db56add638f57a338e20 (diff) | |
| download | skiboot-e59cbfa720845c09b7b601e03dd75b73ab4baf8d.zip skiboot-e59cbfa720845c09b7b601e03dd75b73ab4baf8d.tar.gz skiboot-e59cbfa720845c09b7b601e03dd75b73ab4baf8d.tar.bz2 | |
xive/p10: Activate split mode for PHB ESBs when PQ_disable is available
1/3rd of the cache is reserved for PHB ESBs and the rest to IPIs.
This is sufficient to keep all the PHB ESBs in cache and avoid ESB
cache misses during IO interrupt processing.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
| -rw-r--r-- | hw/xive2.c | 25 | ||||
| -rw-r--r-- | include/xive2-regs.h | 5 |
2 files changed, 30 insertions, 0 deletions
@@ -1601,6 +1601,29 @@ static bool xive_cfg_save_restore(struct xive *x) return !!(x->config & CQ_XIVE_CFG_EN_VP_SAVE_RESTORE); } +/* + * When PQ_disable is available, configure the ESB cache to improve + * performance for PHB ESBs. + * + * split_mode : + * 1/3rd of the cache is reserved for PHB ESBs and the rest to + * IPIs. This is sufficient to keep all the PHB ESBs in cache and + * avoid ESB cache misses during IO interrupt processing. + */ +static void xive_config_esb_cache(struct xive *x) +{ + uint64_t val = xive_regr(x, VC_ESBC_CFG); + + if (xive_has_cap(x, CQ_XIVE_CAP_PHB_PQ_DISABLE)) { + val |= VC_ESBC_CFG_SPLIT_MODE; + xive_dbg(x, "ESB cache configured with split mode. " + "VC_ESBC_CFG=%016llx\n", val); + } else + val &= ~VC_ESBC_CFG_SPLIT_MODE; + + xive_regw(x, VC_ESBC_CFG, val); +} + static void xive_config_fused_core(struct xive *x) { uint64_t val = xive_regr(x, TCTXT_CFG); @@ -1716,6 +1739,8 @@ static bool xive_config_init(struct xive *x) xive_config_fused_core(x); + xive_config_esb_cache(x); + xive_config_reduced_priorities_fixup(x); return true; diff --git a/include/xive2-regs.h b/include/xive2-regs.h index ad1a9b7..4638c3d 100644 --- a/include/xive2-regs.h +++ b/include/xive2-regs.h @@ -227,6 +227,11 @@ #define VC_ESBC_FLUSH_POLL_BLOCK_ID_MASK PPC_BITMASK(32,35) #define VC_ESBC_FLUSH_POLL_OFFSET_MASK PPC_BITMASK(36,63) /* 28-bit */ +/* ESBC configuration */ +#define X_VC_ESBC_CFG 0x148 +#define VC_ESBC_CFG 0x240 +#define VC_ESBC_CFG_SPLIT_MODE PPC_BIT(56) + /* EASC flush control register */ #define X_VC_EASC_FLUSH_CTRL 0x160 #define VC_EASC_FLUSH_CTRL 0x300 |