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| author | Reza Arbab <arbab@linux.vnet.ibm.com> | 2017-11-13 16:19:16 -0600 |
|---|---|---|
| committer | Stewart Smith <stewart@linux.vnet.ibm.com> | 2017-11-13 17:47:56 -0600 |
| commit | ac6f1599ff330fa602b3c9557a08f31f1158a55f (patch) | |
| tree | 34154a2aa7f5efbbefc6a14489a46cfae615bec0 | |
| parent | d6f2505b15422e3c63932a67278ebdbca67047d5 (diff) | |
| download | skiboot-ac6f1599ff330fa602b3c9557a08f31f1158a55f.zip skiboot-ac6f1599ff330fa602b3c9557a08f31f1158a55f.tar.gz skiboot-ac6f1599ff330fa602b3c9557a08f31f1158a55f.tar.bz2 | |
npu2: hw-procedures: Add phy_rx_clock_sel()
Change the RX clk mux control to be done by software instead of HW. This
avoids glitches caused by changing the mux setting.
Signed-off-by: Reza Arbab <arbab@linux.vnet.ibm.com>
Reviewed-By: Alistair Popple <alistair@popple.id.au>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
| -rw-r--r-- | hw/npu2-hw-procedures.c | 20 | ||||
| -rw-r--r-- | include/npu2-regs.h | 1 |
2 files changed, 20 insertions, 1 deletions
diff --git a/hw/npu2-hw-procedures.c b/hw/npu2-hw-procedures.c index 85c2427..3315e74 100644 --- a/hw/npu2-hw-procedures.c +++ b/hw/npu2-hw-procedures.c @@ -578,6 +578,23 @@ static uint32_t phy_rx_dccal_complete(struct npu2_dev *ndev) return PROCEDURE_NEXT; } +static uint32_t phy_rx_clock_sel(struct npu2_dev *ndev) +{ + /* + * Change the RX clk mux control to be done by software instead of HW. This + * avoids glitches caused by changing the mux setting. + * + * Work around a known DL bug by doing these writes twice. + */ + npu2_write_mask_4b(ndev->npu, NPU2_NTL_DL_CLK_CTRL(ndev), 0x80000003, 0x80000003); + npu2_write_mask_4b(ndev->npu, NPU2_NTL_DL_CLK_CTRL(ndev), 0x80000003, 0x80000003); + + npu2_write_mask_4b(ndev->npu, NPU2_NTL_DL_CLK_CTRL(ndev), 0x80000001, 0x80000003); + npu2_write_mask_4b(ndev->npu, NPU2_NTL_DL_CLK_CTRL(ndev), 0x80000001, 0x80000003); + + return PROCEDURE_NEXT; +} + /* Procedure 1.2.5 - IO PHY Tx FIFO Init */ static uint32_t phy_tx_fifo_init(struct npu2_dev *ndev) { @@ -594,7 +611,8 @@ static uint32_t phy_tx_fifo_init(struct npu2_dev *ndev) /* We group TX FIFO init in here mainly because that's what was done * on NVLink1 */ -DEFINE_PROCEDURE(phy_rx_dccal, phy_rx_dccal_complete, phy_tx_fifo_init); +DEFINE_PROCEDURE(phy_rx_dccal, phy_rx_dccal_complete, phy_rx_clock_sel, + phy_tx_fifo_init); /* Procedure 1.2.7 - I/O PHY Upstream Link Training */ static uint32_t phy_rx_training(struct npu2_dev *ndev) diff --git a/include/npu2-regs.h b/include/npu2-regs.h index 307e93b..88ba709 100644 --- a/include/npu2-regs.h +++ b/include/npu2-regs.h @@ -281,6 +281,7 @@ void npu2_write_mask(struct npu2 *p, uint64_t reg, uint64_t val, uint64_t mask); #define NPU2_NTL_CQ_FENCE_STATUS(ndev) NPU2_NTLU_REG_OFFSET(ndev, 0x500) #define NPU2_NTL_DL_CONTROL(ndev) NPU2_DL_REG_OFFSET(ndev, 0xFFF4) #define NPU2_NTL_DL_CONFIG(ndev) NPU2_DL_REG_OFFSET(ndev, 0xFFF8) +#define NPU2_NTL_DL_CLK_CTRL(ndev) NPU2_DL_REG_OFFSET(ndev, 0x001C) /* Misc block registers. Unlike the SM/CTL/DAT/NTL registers above * there is only a single instance of each of these in the NPU so we |